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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-05-20 06:38:47 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-05-20 06:38:47 +0000 |
| commit | 691ae3388f01473d0c4486fa2aa4dba92021387c (patch) | |
| tree | 812a7ea9135e8497b41912edb76fb56933106df2 /llvm/lib/Target/ARM/ARMISelLowering.cpp | |
| parent | 4fd0e4f4157757e4bec452bd8f27ef14e4e36659 (diff) | |
| download | bcm5719-llvm-691ae3388f01473d0c4486fa2aa4dba92021387c.tar.gz bcm5719-llvm-691ae3388f01473d0c4486fa2aa4dba92021387c.zip | |
Use the right register class for LDRrs.
llvm-svn: 157152
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 48cad6173b1..4d78ec256c9 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -5847,7 +5847,7 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const { const TargetRegisterClass *TRC = Subtarget->isThumb() ? (const TargetRegisterClass*)&ARM::tGPRRegClass : - (const TargetRegisterClass*)&ARM::GPRRegClass; + (const TargetRegisterClass*)&ARM::GPRnopcRegClass; // Get a mapping of the call site numbers to all of the landing pads they're // associated with. |
