summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM/ARMISelLowering.cpp
Commit message (Collapse)AuthorAgeFilesLines
* Reduce indentation.Bob Wilson2010-06-251-8/+7
| | | | llvm-svn: 106819
* Do not do tail calls to external symbols. If theDale Johannesen2010-06-231-12/+9
| | | | | | | | | | | branch turns out to be ARM-to-Thumb or vice versa the linker cannot resolve this. 8120438. If this optimization is going to be useful we probably need a compiler flag "assume callees are same architecture" or something like that. llvm-svn: 106662
* When using libcall expansions for the atomic intrinsics, the explicitJim Grosbach2010-06-231-0/+2
| | | | | | | MEMBARRIER fences aren't necessary for ARM. Tell the combiner to fold them away. llvm-svn: 106631
* sign_extend_inreg needs to be expanded for pre-v6 Thumb as well as ARM.Bob Wilson2010-06-211-1/+1
| | | | | | Radar 8104310. llvm-svn: 106484
* Fix error message to match function name.Bob Wilson2010-06-191-1/+1
| | | | llvm-svn: 106381
* Disable sibcall optimization for Thumb1 for now since ↵Evan Cheng2010-06-191-8/+17
| | | | | | Thumb1RegisterInfo::emitEpilogue is not expecting them. llvm-svn: 106368
* back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set)Jim Grosbach2010-06-181-0/+4
| | | | llvm-svn: 106342
* Enable Expand handling of atomics for subtargets that can't do them inline.Jim Grosbach2010-06-181-3/+39
| | | | llvm-svn: 106336
* Enable tail calls on ARM by default, with someDale Johannesen2010-06-181-1/+1
| | | | | | | | | | | | | | basic tests. This has been well tested on Darwin but not elsewhere. It should work provided the linker correctly resolves B.W <label in other function> which it has not seen before, at least from llvm-based compilers. I'm leaving the arm-tail-calls switch in until I see if there's any problems because of that; it might need to be disabled for some environments. llvm-svn: 106299
* Last round of changes for ARM tail calls.Dale Johannesen2010-06-181-7/+14
| | | | | | Not turning them on yet. llvm-svn: 106295
* Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86Jakob Stoklund Olesen2010-06-181-1/+1
| | | | | | | does for {flags}. If we create virtual registers of the CCR class, RegAllocFast may try to spill them, and we can't do that. llvm-svn: 106289
* Thumb1 and any pre-v6 ARM target should use the libcall expansion ofJim Grosbach2010-06-171-1/+6
| | | | | | ISD::MEMBARRIER. v7 and v7 ARM mode continue to use the custom lowering. llvm-svn: 106204
* simplify code a bit and add a more explanatory assert for cases thatJim Grosbach2010-06-171-15/+11
| | | | | | previously would result in 'cannot yet select' errors. llvm-svn: 106199
* format and 80-column cleanupJim Grosbach2010-06-161-5/+4
| | | | llvm-svn: 106173
* Remove the hidden "neon-reg-sequence" option. The reg sequences are workingBob Wilson2010-06-161-4/+1
| | | | | | now, so there's no need to disable them. llvm-svn: 106155
* Make post-ra scheduling, anti-dep breaking, and register scavenger ↵Evan Cheng2010-06-161-1/+6
| | | | | | (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. llvm-svn: 106091
* Next round of tail call changes. Register used in a tailDale Johannesen2010-06-151-5/+8
| | | | | | | | call must not be callee-saved; following x86, add a new regclass to represent this. Also fixes a couple of bugs. Still disabled by default; Thumb doesn't work yet. llvm-svn: 106053
* Add basic support for NEON modified immediates besides VMOV.Bob Wilson2010-06-151-4/+15
| | | | llvm-svn: 106030
* Rename functions referring to VMOV immediates to refer to NEON "modifiedBob Wilson2010-06-141-17/+21
| | | | | | | | immediate" operands. These functions have so far only been used for VMOV but they also apply to other NEON instructions with modified immediate operands. No functional changes. llvm-svn: 105969
* Add a missing bitcast. This code used to only handle conversions betweenBob Wilson2010-06-111-1/+2
| | | | | | | i64 and f64 types, but now it also handle Neon vector types, so the f64 result of VMOVDRR may need to be converted to a Neon type. Radar 8084742. llvm-svn: 105845
* Add instruction encoding for the Neon VMOV immediate instruction. This changesBob Wilson2010-06-111-26/+89
| | | | | | | | | | | the machine instruction representation of the immediate value to be encoded into an integer with similar fields as the actual VMOV instruction. This makes things easier for the disassembler, since it can just stuff the bits into the immediate operand, but harder for the asm printer since it has to decode the value to be printed. Testcase for the encoding will follow later when MC has more support for ARM. llvm-svn: 105836
* Further changes for Neon vector shuffles:Bob Wilson2010-06-071-52/+56
| | | | | | | | | | - change isShuffleMaskLegal to show that all shuffles with 32-bit and 64-bit elements are legal - the Neon shuffle instructions do not support 64-bit elements, but we were not checking for that before lowering shuffles to use them - remove some 64-bit element vduplane patterns that are no longer needed llvm-svn: 105586
* Improvements to tail call code. No functional effectDale Johannesen2010-06-051-20/+22
| | | | | | unless using -arm-tail-calls. llvm-svn: 105515
* More thoroughly disable tails calls by default.Dale Johannesen2010-06-041-3/+3
| | | | | | 8060143, although this doesn't fix the real problem with tail call. llvm-svn: 105472
* For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs andBob Wilson2010-06-041-19/+16
| | | | | | | | | | | VECTOR_SHUFFLEs to REG_SEQUENCE instructions. The standard ISD::BUILD_VECTOR node corresponds closely to REG_SEQUENCE but I couldn't use it here because its operands do not get legalized. That is pretty awful, but I guess it makes sense for other targets. Instead, I have added an ARM-specific version of BUILD_VECTOR that will have its operands properly legalized. This fixes the rest of Radar 7872877. llvm-svn: 105439
* Early implementation of tail call for ARM.Dale Johannesen2010-06-031-6/+230
| | | | | | | | | A temporary flag -arm-tail-calls defaults to off, so there is no functional change by default. Intrepid users may try this; simple cases work but there are bugs. llvm-svn: 105413
* Clean up 80 column violations. No functional change.Jim Grosbach2010-06-021-3/+4
| | | | llvm-svn: 105350
* Schedule high latency instructions for latency reduction even if they are ↵Evan Cheng2010-05-281-1/+19
| | | | | | not vfp / NEON instructions. llvm-svn: 105060
* Update the saved stack pointer in the sjlj function context following eitherJim Grosbach2010-05-271-5/+1
| | | | | | an alloca() or an llvm.stackrestore(). rdar://8031573 llvm-svn: 104900
* back out 104862/104869. Can reuse stacksave after all. Very cool.Jim Grosbach2010-05-271-8/+0
| | | | llvm-svn: 104897
* add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EHJim Grosbach2010-05-271-0/+8
| | | | | | to update the jmpbuf in the presence of VLAs. llvm-svn: 104862
* Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry inJim Grosbach2010-05-261-6/+12
| | | | | | ISD::. No functional change. llvm-svn: 104734
* Clean up indentation.Bob Wilson2010-05-251-2/+2
| | | | llvm-svn: 104580
* LR is in GPR, not tGPR even in Thumb1 mode.Evan Cheng2010-05-241-4/+1
| | | | llvm-svn: 104518
* VDUP doesn't support vectors with 64-bit elements.Bob Wilson2010-05-231-2/+2
| | | | llvm-svn: 104455
* Implement @llvm.returnaddress. rdar://8015977.Evan Cheng2010-05-221-2/+27
| | | | llvm-svn: 104421
* Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.Jim Grosbach2010-05-221-0/+9
| | | | | | | Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match longjmp. llvm-svn: 104419
* Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented byBob Wilson2010-05-221-29/+72
| | | | | | | | copying VFP subregs. This exposed a bunch of dead code in the *spill-q.ll tests, so I tweaked those tests to keep that code from being optimized away. Radar 7872877. llvm-svn: 104415
* Change ARM scheduling default to list-hybrid if the target supports floating ↵Evan Cheng2010-05-211-1/+4
| | | | | | point instructions (and is not using soft float). llvm-svn: 104307
* Allow targets more controls on what nodes are scheduled by reg pressure, ↵Evan Cheng2010-05-201-0/+10
| | | | | | what for latency in hybrid mode. llvm-svn: 104293
* Handle Neon v2f64 and v2i64 vector shuffles as register copies.Bob Wilson2010-05-201-0/+18
| | | | | | This fixes the remaining issue with pr7167. llvm-svn: 104257
* Code refactoring: pull SchedPreference enum from TargetLowering.h to ↵Evan Cheng2010-05-191-1/+1
| | | | | | TargetMachine.h and put it in its own namespace. llvm-svn: 104147
* Sink dag combine's post index load / store code that swap base ptr and index ↵Evan Cheng2010-05-181-1/+15
| | | | | | into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 llvm-svn: 104060
* Generalize the ARM DAG combiner of mul with constants to all power-of-two cases.Anton Korobeynikov2010-05-161-34/+21
| | | | llvm-svn: 103901
* Some cheap DAG combine goodness for multiplication with a particular constant.Anton Korobeynikov2010-05-151-0/+71
| | | | | | This can be extended later on to handle more "complex" constants. llvm-svn: 103881
* v4i64 and v8i64 are only synthesizable when NEON is available.Evan Cheng2010-05-151-4/+6
| | | | llvm-svn: 103855
* Allow TargetLowering::getRegClassFor() to be called on illegal types. AlsoEvan Cheng2010-05-151-7/+13
| | | | | | | allow target to override it in order to map register classes to illegal but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON. llvm-svn: 103854
* Added a QQQQ register file to model 4-consecutive Q registers.Evan Cheng2010-05-141-1/+3
| | | | llvm-svn: 103760
* Implement a bunch more TargetSelectionDAGInfo infrastructure.Dan Gohman2010-05-111-110/+0
| | | | | | | | Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and EmitTargetCodeForMemmove out of TargetLowering and into SelectionDAGInfo to exercise this. llvm-svn: 103481
* Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction.Evan Cheng2010-05-111-0/+2
| | | | llvm-svn: 103459
OpenPOWER on IntegriCloud