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* Optimize a couple of common patterns involving conditional moves where the falseEvan Cheng2012-02-231-5/+88
| | | | | | | | | | | | | | | | | | | | | value is zero. Instead of a cmov + op, issue an conditional op instead. e.g. cmp r9, r4 mov r4, #0 moveq r4, #1 orr lr, lr, r4 should be: cmp r9, r4 orreq lr, lr, #1 That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y). It's possible to extend this to ADD and SUB but I don't think they are common. rdar://8659097 llvm-svn: 151224
* Make all pointers to TargetRegisterClass const since they are all pointers ↵Craig Topper2012-02-221-7/+7
| | | | | | to static data that should not be modified. llvm-svn: 151134
* Proper support for a bastardized darwin-eabi hybird ABI.Evan Cheng2012-02-211-1/+1
| | | | llvm-svn: 151083
* Improve generated code for extending loads and some trunc stores on ARM.James Molloy2012-02-201-7/+29
| | | | | | Teach TargetSelectionDAG about lengthening loads for vector types and set v4i8 as legal. Allow FP_TO_UINT for v4i16 from v4i32. llvm-svn: 150956
* Don't reserve the R0 and R1 registers here. We don't use these registers, andBill Wendling2012-02-131-4/+9
| | | | | | | marking them as "live-in" into a BB ruins some invariants that the back-end tries to maintain. llvm-svn: 150437
* Make valgrind happy.Jason W Kim2012-02-101-2/+2
| | | | llvm-svn: 150251
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-071-10/+7
| | | | llvm-svn: 149961
* Cleanups for EABI standard functionsAnton Korobeynikov2012-01-291-2/+7
| | | | llvm-svn: 149195
* Use base AAPCS for varargs functions even for AAPCS-VFP CCAnton Korobeynikov2012-01-291-1/+3
| | | | llvm-svn: 149194
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-6/+2
| | | | llvm-svn: 148578
* Refactor variables unused under non-assert builds (& remove two entirely ↵David Blaikie2012-01-161-2/+2
| | | | | | unused variables). llvm-svn: 148230
* Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through ↵Benjamin Kramer2012-01-151-20/+12
| | | | | | CodeGen. llvm-svn: 148218
* Match SelectionDAG logic for enabling movt.Jakob Stoklund Olesen2012-01-071-1/+2
| | | | | | Darwin doesn't do static, and ELF targets only support static. llvm-svn: 147740
* Remove VectorExtras. This unused helper was written for a type of API that ↵Benjamin Kramer2012-01-071-1/+0
| | | | | | is discouraged now. llvm-svn: 147738
* Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138>Bob Wilson2011-12-221-1/+6
| | | | | | | | | | | My change r146949 added register clobbers to the eh_sjlj_dispatchsetup pseudo instruction, but on Thumb1 some of those registers cannot be used. This caused massive failures on the testsuite when compiling for Thumb1. While fixing that, I noticed that the eh_sjlj_setjmp instruction has a "nofp" variant, and I realized that dispatchsetup needs the same thing, so I have added that as well. llvm-svn: 147204
* Make check a bit more strict so we don't call ARM_AM::getFP32Imm with a ↵Eli Friedman2011-12-151-1/+1
| | | | | | value that isn't a 32-bit value. (This is just to be safe; I don't think this actually causes any issues in practice.) llvm-svn: 146700
* Initial CodeGen support for CTTZ/CTLZ where a zero input produces anChandler Carruth2011-12-131-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | undefined result. This adds new ISD nodes for the new semantics, selecting them when the LLVM intrinsic indicates that the undef behavior is desired. The new nodes expand trivially to the old nodes, so targets don't actually need to do anything to support these new nodes besides indicating that they should be expanded. I've done this for all the operand types that I could figure out for all the targets. Owners of various targets, please review and let me know if any of these are incorrect. Note that the expand behavior is *conservatively correct*, and exactly matches LLVM's current behavior with these operations. Ideally this patch will not change behavior in any way. For example the regtest suite finds the exact same instruction sequences coming out of the code generator. That's why there are no new tests here -- all of this is being exercised by the existing test suite. Thanks to Duncan Sands for reviewing the various bits of this patch and helping me get the wrinkles ironed out with expanding for each target. Also thanks to Chris for clarifying through all the discussions that this is indeed the approach he was looking for. That said, there are likely still rough spots. Further review much appreciated. llvm-svn: 146466
* Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix ↵Stepan Dyatkovskiy2011-12-111-0/+22
| | | | | | for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Third attempt: simplified checks in test for armv7-apple-darwin11. llvm-svn: 146341
* Revert r146322 to appease buildbots. Original commit message:Chad Rosier2011-12-101-22/+0
| | | | | | | | Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt. llvm-svn: 146328
* Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix ↵Stepan Dyatkovskiy2011-12-101-0/+22
| | | | | | for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt. llvm-svn: 146322
* Splats can contain undef's; make sure to handle them correctly. PR11526.Eli Friedman2011-12-091-2/+1
| | | | llvm-svn: 146299
* Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsicsDaniel Dunbar2011-12-081-22/+0
| | | | | | | sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).", it is failing tests. llvm-svn: 146157
* Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix ↵Stepan Dyatkovskiy2011-12-081-0/+22
| | | | | | for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). llvm-svn: 146143
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-4/+4
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-021-9/+14
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* Move code into anonymous namespaces.Benjamin Kramer2011-11-261-1/+1
| | | | llvm-svn: 145154
* Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602>Bob Wilson2011-11-161-59/+2
| | | | | | | | | | | | | | | | | The EmitBasePointerRecalculation function has 2 problems, one minor and one fatal. The minor problem is that it inserts the code at the setjmp instead of in the dispatch block. The fatal problem is that at the point where this code runs, we don't know whether there will be a base pointer, so the entire function is a no-op. The base pointer recalculation needs to be handled as it was before, by inserting a pseudo instruction that gets expanded late. Most of the support for the old approach is still here, but it no longer has any connection to the eh_sjlj_dispatchsetup intrinsic. Clean up the parts related to the intrinsic and just generate the pseudo instruction directly. llvm-svn: 144781
* Remove some unnecessary includes of PseudoSourceValue.h.Jay Foad2011-11-151-1/+0
| | | | llvm-svn: 144631
* Add vmov.f32 to materialize f32 immediate splats which cannot be handled byEvan Cheng2011-11-151-0/+11
| | | | | | integer variants. rdar://10437054 llvm-svn: 144608
* Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3.Eli Friedman2011-11-111-0/+1
| | | | llvm-svn: 144361
* Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM.Eli Friedman2011-11-091-1/+25
| | | | llvm-svn: 144241
* Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported.Lang Hames2011-11-081-0/+7
| | | | | | | | Add support for trimming constants to GetDemandedBits. This fixes some funky constant generation that occurs when stores are expanded for targets that don't support unaligned stores natively. llvm-svn: 144102
* Added invariant field to the DAG.getLoad method and changed all calls.Pete Cooper2011-11-081-31/+36
| | | | | | When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses llvm-svn: 144100
* Make sure to mark vector extload's as expand on ARM. Fixes PR11319.Eli Friedman2011-11-081-9/+11
| | | | llvm-svn: 144057
* Reapply r143206, with fixes. Disallow physical register lifetimesDan Gohman2011-11-031-3/+16
| | | | | | | across calls, and only check for nested dependences on the special call-sequence-resource register. llvm-svn: 143660
* Fixed parameter name.Lang Hames2011-11-021-2/+2
| | | | llvm-svn: 143594
* Try to lower memset/memcpy/memmove to vector instructions on ARM where the ↵Lang Hames2011-11-021-0/+28
| | | | | | alignment permits. llvm-svn: 143582
* Revert r143206, as there are still some failing tests.Dan Gohman2011-10-291-16/+3
| | | | llvm-svn: 143262
* Reapply r143177 and r143179 (reverting r143188), with schedulerDan Gohman2011-10-281-3/+16
| | | | | | | | | fixes: Use a separate register, instead of SP, as the calling-convention resource, to avoid spurious conflicts with actual uses of SP. Also, fix unscheduling of calling sequences, which can be triggered by pseudo-two-address dependencies. llvm-svn: 143206
* Speculatively disable Dan's commits 143177 and 143179 to see ifDuncan Sands2011-10-281-16/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | it fixes the dragonegg self-host (it looks like gcc is miscompiled). Original commit messages: Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW on every node as it legalizes them. This makes it easier to use hasOneUse() heuristics, since unneeded nodes can be removed from the DAG earlier. Make LegalizeOps visit the DAG in an operands-last order. It previously used operands-first, because LegalizeTypes has to go operands-first, and LegalizeTypes used to be part of LegalizeOps, but they're now split. The operands-last order is more natural for several legalization tasks. For example, it allows lowering code for nodes with floating-point or vector constants to see those constants directly instead of seeing the lowered form (often constant-pool loads). This makes some things somewhat more complicated today, though it ought to allow things to be simpler in the future. It also fixes some bugs exposed by Legalizing using RAUW aggressively. Remove the part of LegalizeOps that attempted to patch up invalid chain operands on libcalls generated by LegalizeTypes, since it doesn't work with the new LegalizeOps traversal order. Instead, define what LegalizeTypes is doing to be correct, and transfer the responsibility of keeping calls from having overlapping calling sequences into the scheduler. Teach the scheduler to model callseq_begin/end pairs as having a physical register definition/use to prevent calls from having overlapping calling sequences. This is also somewhat complicated, though there are ways it might be simplified in the future. This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others. Please direct high-level questions about this patch to management. Delete #if 0 code accidentally left in. llvm-svn: 143188
* Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUWDan Gohman2011-10-281-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on every node as it legalizes them. This makes it easier to use hasOneUse() heuristics, since unneeded nodes can be removed from the DAG earlier. Make LegalizeOps visit the DAG in an operands-last order. It previously used operands-first, because LegalizeTypes has to go operands-first, and LegalizeTypes used to be part of LegalizeOps, but they're now split. The operands-last order is more natural for several legalization tasks. For example, it allows lowering code for nodes with floating-point or vector constants to see those constants directly instead of seeing the lowered form (often constant-pool loads). This makes some things somewhat more complicated today, though it ought to allow things to be simpler in the future. It also fixes some bugs exposed by Legalizing using RAUW aggressively. Remove the part of LegalizeOps that attempted to patch up invalid chain operands on libcalls generated by LegalizeTypes, since it doesn't work with the new LegalizeOps traversal order. Instead, define what LegalizeTypes is doing to be correct, and transfer the responsibility of keeping calls from having overlapping calling sequences into the scheduler. Teach the scheduler to model callseq_begin/end pairs as having a physical register definition/use to prevent calls from having overlapping calling sequences. This is also somewhat complicated, though there are ways it might be simplified in the future. This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others. Please direct high-level questions about this patch to management. llvm-svn: 143177
* Make sure short memsets on ARM lower to stores, even when optimizing for size.Lang Hames2011-10-261-0/+2
| | | | llvm-svn: 143055
* Revert r142530 at least temporarily while a discussion is had on ↵James Molloy2011-10-261-5/+2
| | | | | | llvm-commits regarding exactly how much optsize should optimize for size over performance. llvm-svn: 143023
* Use a worklist to prevent the iterator from becoming invalidated because of ↵Bill Wendling2011-10-261-3/+4
| | | | | | the 'removeSuccessor' call. Noticed in a Release+Asserts+Check buildbot. llvm-svn: 143018
* Revert part of r142530. The patch potentially hurts performance especiallyEvan Cheng2011-10-261-3/+3
| | | | | | | on Darwin platforms where -Os means optimize for size without hurting performance. llvm-svn: 143002
* Don't crash on variable insertelement on ARM. PR10258.Eli Friedman2011-10-241-0/+11
| | | | llvm-svn: 142871
* Change this overloaded use of Sched::Latency to be an overloadedDan Gohman2011-10-241-2/+2
| | | | | | use of Sched::ILP instead, as Sched::Latency is going away. llvm-svn: 142813
* The different flavors of ARM have different valid subsets of registers. CheckBill Wendling2011-10-221-3/+13
| | | | | | | that the set of callee-saved registers is correct for the specific platform. <rdar://problem/10313708> & ctor_dtor_count & ctor_dtor_count-2 llvm-svn: 142706
* Add missing operand. <rdar://problem/10313323>Bill Wendling2011-10-201-1/+2
| | | | llvm-svn: 142615
* Use literal pool loads instead of MOVW/MOVT for materializing global ↵James Molloy2011-10-191-3/+6
| | | | | | | | | | | | | | addresses when optimizing for size. On spec/gcc, this caused a codesize improvement of ~1.9% for ARM mode and ~4.9% for Thumb(2) mode. This is codesize including literal pools. The pools themselves doubled in size for ARM mode and quintupled for Thumb mode, leaving suggestion that there is still perhaps redundancy in LLVM's use of constant pools that could be decreased by sharing entries. Fixes PR11087. llvm-svn: 142530
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