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authorDan Gohman <gohman@apple.com>2011-10-24 17:55:11 +0000
committerDan Gohman <gohman@apple.com>2011-10-24 17:55:11 +0000
commit4ed1afa51dfa574202325598e17093a9fc41970d (patch)
tree213895e5a5039aa7c02efeb58f4613c5df9d4e1d /llvm/lib/Target/ARM/ARMISelLowering.cpp
parent2790870de0fd249b1da628681676a25c020bbed2 (diff)
downloadbcm5719-llvm-4ed1afa51dfa574202325598e17093a9fc41970d.tar.gz
bcm5719-llvm-4ed1afa51dfa574202325598e17093a9fc41970d.zip
Change this overloaded use of Sched::Latency to be an overloaded
use of Sched::ILP instead, as Sched::Latency is going away. llvm-svn: 142813
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMISelLowering.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 72ea6ace522..422a40fa6d8 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -986,7 +986,7 @@ Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
if (VT == MVT::Glue || VT == MVT::Other)
continue;
if (VT.isFloatingPoint() || VT.isVector())
- return Sched::Latency;
+ return Sched::ILP;
}
if (!N->isMachineOpcode())
@@ -1001,7 +1001,7 @@ Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
return Sched::RegPressure;
if (!Itins->isEmpty() &&
Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
- return Sched::Latency;
+ return Sched::ILP;
return Sched::RegPressure;
}
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