| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | Add comment, clean up code. No functional change. | Jakob Stoklund Olesen | 2012-08-17 | 1 | -30/+39 |
| * | Handle ARM MOVCC optimization in PeepholeOptimizer. | Jakob Stoklund Olesen | 2012-08-16 | 1 | -48/+0 |
| * | Fold predicable instructions into MOVCC / t2MOVCC. | Jakob Stoklund Olesen | 2012-08-15 | 1 | -0/+48 |
| * | Use vld1/vst1 to load/store f64 if alignment is < 4 and the target allows una... | Evan Cheng | 2012-08-15 | 1 | -0/+2 |
| * | Do not optimize (or (and X,Y), Z) into BFI and other sequences if the AND ISD... | Nadav Rotem | 2012-08-13 | 1 | -1/+5 |
| * | Revert 161581: Patch to implement UMLAL/SMLAL instructions for the ARM | Arnold Schwaighofer | 2012-08-12 | 1 | -156/+0 |
| * | Change addTypeForNeon to use MVT instead of EVT so all the calls to getSimple... | Craig Topper | 2012-08-12 | 1 | -48/+43 |
| * | Patch to implement UMLAL/SMLAL instructions for the ARM architecture | Arnold Schwaighofer | 2012-08-09 | 1 | -0/+156 |
| * | Fall back to selection DAG isel for calls to builtin functions. | Bob Wilson | 2012-08-03 | 1 | -2/+3 |
| * | Add support for the ARM GHC calling convention, this patch was in 3.0, | Eric Christopher | 2012-08-03 | 1 | -0/+2 |
| * | ARM: Don't assume an SDNode is a constant. | Jim Grosbach | 2012-07-25 | 1 | -0/+4 |
| * | Fix ARMTargetLowering::isLegalAddImmediate to consider thumb encodings. | Andrew Trick | 2012-07-18 | 1 | -4/+11 |
| * | whitespace | Andrew Trick | 2012-07-18 | 1 | -2/+2 |
| * | ARM: use NOEN loads and stores if possible when handling struct byval. | Manman Ren | 2012-06-18 | 1 | -8/+42 |
| * | ARM: optimization for sub+abs. | Manman Ren | 2012-06-15 | 1 | -11/+6 |
| * | Re-enable the CMN instruction. | Bill Wendling | 2012-06-11 | 1 | -0/+1 |
| * | ARM: properly handle alignment for struct byval. | Manman Ren | 2012-06-01 | 1 | -246/+268 |
| * | ARM: support struct byval in llvm | Manman Ren | 2012-06-01 | 1 | -15/+262 |
| * | Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall | Justin Holewinski | 2012-05-25 | 1 | -9/+16 |
| * | Use the right register class for LDRrs. | Jakob Stoklund Olesen | 2012-05-20 | 1 | -1/+1 |
| * | Add a new target hook "predictableSelectIsExpensive". | Benjamin Kramer | 2012-05-05 | 1 | -0/+3 |
| * | Pacify GCC's -Wreturn-type | Matt Beaumont-Gay | 2012-05-04 | 1 | -0/+1 |
| * | Make ARM and Mips use TargetMachine::getTLSModel() | Hans Wennborg | 2012-05-04 | 1 | -8/+15 |
| * | Don't introduce illegal types when creating vmull operations. <rdar://11324364> | Bob Wilson | 2012-04-30 | 1 | -1/+3 |
| * | Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change s... | Craig Topper | 2012-04-20 | 1 | -69/+74 |
| * | Handle llvm.fma.* intrinsics. rdar://10914096 | Evan Cheng | 2012-04-10 | 1 | -2/+4 |
| * | Fix a long standing tail call optimization bug. When a libcall is emitted | Evan Cheng | 2012-04-10 | 1 | -33/+42 |
| * | When performing a truncating store, it's possible to rearrange the data | Chad Rosier | 2012-04-09 | 1 | -1/+85 |
| * | Update comments and remove unnecessary isVolatile() check. | Chad Rosier | 2012-04-09 | 1 | -3/+5 |
| * | Tidy up. 80 columns. | Jim Grosbach | 2012-04-06 | 1 | -1/+2 |
| * | There is no portable std::abs overload for int64_t, use the llvm::abs64 | Chandler Carruth | 2012-04-06 | 1 | -2/+2 |
| * | Allow negative immediates in ARM and Thumb2 compares. | Jakob Stoklund Olesen | 2012-04-06 | 1 | -2/+4 |
| * | Always compute all the bits in ComputeMaskedBits. | Rafael Espindola | 2012-04-04 | 1 | -7/+4 |
| * | ARM target should allow codegenprep to duplicate ret instructions to enable t... | Evan Cheng | 2012-03-30 | 1 | -1/+1 |
| * | Try using vmov.i32 to materialize FP32 constants that can't be materialized by | Lang Hames | 2012-03-29 | 1 | -23/+54 |
| * | Remove unnecessary llvm:: qualifications | Craig Topper | 2012-03-27 | 1 | -1/+1 |
| * | Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.h | Craig Topper | 2012-03-26 | 1 | -1/+0 |
| * | Replace uses of ARMBaseInstrInfo and ARMTargetMachine with the Base versions. | Craig Topper | 2012-03-25 | 1 | -3/+2 |
| * | Perform mul combine when multiplying wiht negative constants. | Anton Korobeynikov | 2012-03-19 | 1 | -18/+48 |
| * | Reorder includes to match coding standards. Fix an issue or two exposed by that. | Craig Topper | 2012-03-17 | 1 | -2/+1 |
| * | Use vmov.f32 to materialize f32 consts on ARM. This relaxes constraints on | Lang Hames | 2012-03-15 | 1 | -0/+24 |
| * | Convert more static tables of registers used by calling convention to uint16_... | Craig Topper | 2012-03-11 | 1 | -1/+1 |
| * | Use uint16_t to store registers in callee saved register tables to reduce siz... | Craig Topper | 2012-03-04 | 1 | -1/+1 |
| * | Neuter the optimization I implemented with r107852 and r108258 which turn some | Evan Cheng | 2012-03-01 | 1 | -8/+12 |
| * | Re-commit r151623 with fix. Only issue special no-return calls if it's a dire... | Evan Cheng | 2012-02-28 | 1 | -5/+14 |
| * | Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack pre... | Daniel Dunbar | 2012-02-28 | 1 | -14/+5 |
| * | Some ARM implementaions, e.g. A-series, does return stack prediction. That is, | Evan Cheng | 2012-02-28 | 1 | -5/+14 |
| * | Switch ARM target to register masks. | Jakob Stoklund Olesen | 2012-02-24 | 1 | -0/+6 |
| * | When emitting a cmp with 0 for a lowered select, mask out the high | Dan Gohman | 2012-02-24 | 1 | -0/+5 |
| * | Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high 16 bits | Evan Cheng | 2012-02-23 | 1 | -0/+15 |
