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* Replace a few more "fall through" comments with LLVM_FALLTHROUGHJustin Bogner2016-08-171-2/+2
| | | | | | Follow up to r278902. I had missed "fall through", with a space. llvm-svn: 278970
* Replace "fallthrough" comments with LLVM_FALLTHROUGHJustin Bogner2016-08-171-7/+9
| | | | | | | This is a mechanical change of comments in switches like fallthrough, fall-through, or fall-thru to use the LLVM_FALLTHROUGH macro instead. llvm-svn: 278902
* Use the range variant of count_if instead of unpacking begin/endDavid Majnemer2016-08-121-1/+1
| | | | | | No functionality change is intended. llvm-svn: 278474
* Use the range variant of find instead of unpacking begin/endDavid Majnemer2016-08-111-2/+2
| | | | | | | | | If the result of the find is only used to compare against end(), just use is_contained instead. No functionality change is intended. llvm-svn: 278433
* Use range algorithms instead of unpacking begin/endDavid Majnemer2016-08-111-1/+1
| | | | | | No functionality change is intended. llvm-svn: 278417
* [ARM] Add support for embedded position-independent codeOliver Stannard2016-08-081-2/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for some new relocation models to the ARM backend: * Read-only position independence (ROPI): Code and read-only data is accessed PC-relative. The offsets between all code and RO data sections are known at static link time. This does not affect read-write data. * Read-write position independence (RWPI): Read-write data is accessed relative to the static base register (r9). The offsets between all writeable data sections are known at static link time. This does not affect read-only data. These two modes are independent (they specify how different objects should be addressed), so they can be used individually or together. They are otherwise the same as the "static" relocation model, and are not compatible with SysV-style PIC using a global offset table. These modes are normally used by bare-metal systems or systems with small real-time operating systems. They are designed to avoid the need for a dynamic linker, the only initialisation required is setting r9 to an appropriate value for RWPI code. I have only added support to SelectionDAG, not FastISel, because FastISel is currently disabled for bare-metal targets where these modes would be used. Differential Revision: https://reviews.llvm.org/D23195 llvm-svn: 278015
* [ARM] Some saturation instructions not DSP-onlyBernard Ogden2016-08-021-1/+1
| | | | | | | | | | | | | | | | | | | | | Summary: Commit 276701 requires that targets have the DSP extensions to use certain saturating instructions. This requires some corrections. For ARM ISA the instructions in question are available in all v6* architectures. For Thumb2, the instructions in question are available from v6T2. SSAT and USAT are part of the base architecture while SSAT16 and USAT16 require the DSP extensions. Reviewers: rengolin Subscribers: aemerson, rengolin, samparker, llvm-commits Differential Revision: https://reviews.llvm.org/D23010 llvm-svn: 277439
* [Thumb] Emit Thumb move in both Thumb modes for struct_byval predicatesPrakhar Bahuguna2016-07-291-4/+5
| | | | | | | | | | | | | | | | | Summary: The MOV/MOVT instructions being chosen for struct_byval predicates was conditional only on Thumb2, resulting in an ARM MOV/MOVT instruction being incorrectly emitted in Thumb1 mode. This is especially apparent with v8-m.base targets. This patch ensures that Thumb instructions are emitted in both Thumb modes. Reviewers: rengolin, t.p.northover Subscribers: llvm-commits, aemerson, rengolin Differential Revision: https://reviews.llvm.org/D22865 llvm-svn: 277128
* MachineFunction: Return reference for getFrameInfo(); NFCMatthias Braun2016-07-281-25/+25
| | | | | | | getFrameInfo() never returns nullptr so we should use a reference instead of a pointer. llvm-svn: 277017
* [ARM] Saturation instructions are DSP-onlyRenato Golin2016-07-251-1/+2
| | | | | | | | | | | The saturation instructions appeared in v6T2, with DSP extensions, but they were being accepted / generated on any, with the new introduction of the saturation detection in the back-end. This commit restricts the usage to DSP-enable only cores. Fixes PR28607. llvm-svn: 276701
* [ARM] Improve longMAC codegen testSam Parker2016-07-251-1/+2
| | | | | | | | Added thumb targets and dataflow checks to the longMAC test. Differential Revision: https://reviews.llvm.org/D22684 llvm-svn: 276629
* Revert "Disable this-return argument forwarding on ARM/AArch64"David Majnemer2016-07-201-8/+1
| | | | | | | | | Inference of the 'returned' attribute was fixed in r276008, lets try turning the backend support back on. This reverts commit r275677. llvm-svn: 276081
* [ARM] Honour ABI for rem under -O0 for EABI, GNUEABI, Android and MuslDiana Picus2016-07-181-0/+1
| | | | | | | | | | | | | | | | | | | | At higher optimization levels, we generate the libcall for DIVREM_Ix, which is fine: aeabi_{u|i}divmod. At -O0 we generate the one for REM_Ix, which is the default {u}mod{q|h|s|d}i3. This commit makes sure that we don't generate REM_Ix calls for ABIs that don't support them (i.e. where we need to use DIVREM_Ix instead). This is achieved by bailing out of FastISel, which can't handle non-double multi-reg returns, and letting the legalization infrastructure expand the REM_Ix calls. It also updates the divmod-eabi.ll test to run under -O0 as well, and adds some Windows checks to it to make sure we don't break things for it. Fixes PR27068 Differential Revision: https://reviews.llvm.org/D21926 llvm-svn: 275773
* Disable this-return argument forwarding on ARM/AArch64Hal Finkel2016-07-161-1/+8
| | | | | | | | | | | r275042 reverted function-attribute inference for the 'returned' attribute because the feature triggered self-hosting failures on ARM and AArch64. James Molloy determined that the this-return argument forwarding feature, which directly ties the returned input argument to the returned value, was the cause. It seems likely that this forwarding code contains, or triggers, a subtle bug. Disabling for now until we can track that down. llvm-svn: 275677
* [SelectionDAG] Get rid of bool parameters in SelectionDAG::getLoad, ↵Justin Lebar2016-07-151-115/+80
| | | | | | | | | | | | | | | | | | | | | | | getStore, and friends. Summary: Instead, we take a single flags arg (a bitset). Also add a default 0 alignment, and change the order of arguments so the alignment comes before the flags. This greatly simplifies many callsites, and fixes a bug in AMDGPUISelLowering, wherein the order of the args to getLoad was inverted. It also greatly simplifies the process of adding another flag to getLoad. Reviewers: chandlerc, tstellarAMD Subscribers: jholewinski, arsenm, jyknight, dsanders, nemanjai, llvm-commits Differential Revision: http://reviews.llvm.org/D22249 llvm-svn: 275592
* [ARM] Fix build after r275540James Molloy2016-07-151-6/+6
| | | | | | A rebase seemed so innocent before committing. Turns out someone changed a pointer to a reference in the mean time :( llvm-svn: 275541
* [Thumb-1] Select post-increment load and store where possibleJames Molloy2016-07-151-4/+36
| | | | | | | | | | Thumb-1 doesn't have post-inc or pre-inc load or store instructions. However the LDM/STM instructions with writeback can function as post-inc load/store: ldm r0!, {r1} @ load from r0 into r1 and increment r0 by 4 Obviously, this only works if the post increment is 4. llvm-svn: 275540
* [ARM] Followup to r275537 addressing review commentsJames Molloy2016-07-151-2/+2
| | | | | | Address Chad's comment in D22216 which I missed due to tunnel vision on the "LGTM" comment. llvm-svn: 275538
* [ARM] Prefer indirect calls in minsize modeJames Molloy2016-07-151-28/+42
| | | | | | | | ... When we emit several calls to the same function in the same basic block. An indirect call uses a "BLX r0" instruction which has a 16-bit encoding. If many calls are made to the same target, this can enable significant code size reductions. llvm-svn: 275537
* Give helper classes/functions internal linkage. NFC.Benjamin Kramer2016-07-101-9/+14
| | | | llvm-svn: 275014
* ARM: Remove implicit iterator conversions, NFCDuncan P. N. Exon Smith2016-07-081-1/+1
| | | | | | | | | | | Remove remaining implicit conversions from MachineInstrBundleIterator to MachineInstr* from the ARM backend. In most cases, I made them less attractive by preferring MachineInstr& or using a ranged-based for loop. Once all the backends are fixed I'll make the operator explicit so that this doesn't bitrot back. llvm-svn: 274920
* ARM: fix `-mlong-calls` for WoASaleem Abdulrasool2016-07-051-1/+1
| | | | | | | | | Not all code-paths set the relocation model to static for Windows. This currently breaks on Windows ARM with `-mlong-calls` when built with clang. Loosen the assertion to what it was previously. We would ideally ensure that all the configuration sets Windows to static relocation model. llvm-svn: 274570
* [CodeGen,Target] Remove the version of DAG.getVectorShuffle that takes a ↵Craig Topper2016-07-011-3/+3
| | | | | | | | pointer to a mask array. Convert all callers to use the ArrayRef version. No functional change intended. For the most part this simplifies all callers. There were two places in X86 that needed an explicit makeArrayRef to shorten a statically sized array. llvm-svn: 274337
* CodeGen: Use MachineInstr& in TargetLowering, NFCDuncan P. N. Exon Smith2016-06-301-86/+90
| | | | | | | | | | | | | This is a mechanical change to make TargetLowering API take MachineInstr& (instead of MachineInstr*), since the argument is expected to be a valid MachineInstr. In one case, changed a parameter from MachineInstr* to MachineBasicBlock::iterator, since it was used as an insertion point. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. llvm-svn: 274287
* Delete unused includes. NFC.Rafael Espindola2016-06-301-1/+0
| | | | llvm-svn: 274225
* Use ShuffleVectorSDNode::isSplat member method instead of static method ↵Craig Topper2016-06-301-1/+1
| | | | | | isSplatMask where the mask came directly from getMask() on a shuffle node. llvm-svn: 274208
* CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith2016-06-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is mostly a mechanical change to make TargetInstrInfo API take MachineInstr& (instead of MachineInstr* or MachineBasicBlock::iterator) when the argument is expected to be a valid MachineInstr. This is a general API improvement. Although it would be possible to do this one function at a time, that would demand a quadratic amount of churn since many of these functions call each other. Instead I've done everything as a block and just updated what was necessary. This is mostly mechanical fixes: adding and removing `*` and `&` operators. The only non-mechanical change is to split ARMBaseInstrInfo::getOperandLatencyImpl out from ARMBaseInstrInfo::getOperandLatency. Previously, the latter took a `MachineInstr*` which it updated to the instruction bundle leader; now, the latter calls the former either with the same `MachineInstr&` or the bundle leader. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. Note: I updated WebAssembly, Lanai, and AVR (despite being off-by-default) since it turned out to be easy. I couldn't run tests for AVR since llc doesn't link with it turned on. llvm-svn: 274189
* Don't pass a Reloc::Model to GVIsIndirectSymbol.Rafael Espindola2016-06-281-2/+1
| | | | | | | | It already has access to it. While at it, rename it to isGVIndirectSymbol. llvm-svn: 274023
* NFC. Fix popular typo in comment 'deferencing' --> 'dereferencing'.Nick Lewycky2016-06-281-1/+1
| | | | | | Bonus changes, * placement in X86ISelLowering and 'exerce' -> 'exercise' in test. llvm-svn: 273984
* Move shouldAssumeDSOLocal to Target.Rafael Espindola2016-06-271-8/+2
| | | | | | Should fix the shared library build. llvm-svn: 273958
* Refactor a duplicated predicate. NFC.Rafael Espindola2016-06-261-4/+0
| | | | llvm-svn: 273826
* Add support for musl-libc on ARM Linux.Rafael Espindola2016-06-241-3/+3
| | | | | | Patch by Lei Zhang! llvm-svn: 273726
* [ARM] Use aapcs_vfp for ___truncdfhf2 on v7k.Ahmed Bougacha2016-06-241-11/+13
| | | | | | | r215348 overrode the f16 libcalls to be soft-float, but v7k uses the default (hard-float) calling convention. llvm-svn: 273631
* [ARM] Lower (select_cc k k (select_cc ~k ~k x)) into (SSAT l_k x)Pablo Barrio2016-06-231-1/+133
| | | | | | | | | | | | | | | | | Summary: SSAT saturates an integer, making sure that its value lies within an interval [-k, k]. Since the constant is given to SSAT as the number of bytes set to one, k + 1 must be a power of 2, otherwise the optimization is not possible. Also, the select_cc must use < and > respectively so that they define an interval. Reviewers: mcrosier, jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D21372 llvm-svn: 273581
* [ARM] Do not test for CPUs, use SubtargetFeatures (Part 1). NFCIDiana Picus2016-06-231-2/+3
| | | | | | | | | | | | | This is a cleanup commit similar to r271555, but for ARM. The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods. Since the ARM backend seems to have quite a lot of calls to these methods, I intend to submit 5-6 subtarget features at a time, instead of one big lump. Differential Revision: http://reviews.llvm.org/D21432 llvm-svn: 273544
* [SDAG] Remove FixedArgs parameter from CallLoweringInfo::setCalleeKrzysztof Parzyszek2016-06-221-6/+5
| | | | | | | | | | | The setCallee function will set the number of fixed arguments based on the size of the argument list. The FixedArgs parameter was often explicitly set to 0, leading to a lack of consistent value for non- vararg functions. Differential Revision: http://reviews.llvm.org/D20376 llvm-svn: 273403
* [ARM] Enable isel of UMAALSam Parker2016-06-201-7/+86
| | | | | | | | | | TargetLowering and DAGToDAG are used to combine ADDC, ADDE and UMLAL dags into UMAAL. Selection is split into the two phases because it is easier to match the two patterns at those different times. Differential Revision: http://http://reviews.llvm.org/D21461 llvm-svn: 273165
* Add a isPositionIndependent predicate.Rafael Espindola2016-06-201-17/+19
| | | | | | | Reduces a bit of code duplication and clarify where we are interested just on position independence and no the location of the symbol. llvm-svn: 273164
* Don't print (PLT) on arm.Rafael Espindola2016-06-161-12/+2
| | | | | | | | | The R_ARM_PLT32 relocation is deprecated and is not produced by MC. This means that the code being deleted is dead from the .o point of view and was making the .s more confusing. llvm-svn: 272909
* Refactor duplicated code. NFC.Rafael Espindola2016-06-161-3/+1
| | | | llvm-svn: 272905
* Refactor duplicated code. NFC.Rafael Espindola2016-06-161-6/+5
| | | | llvm-svn: 272904
* Refactor duplicated code. NFC.Rafael Espindola2016-06-161-4/+5
| | | | llvm-svn: 272903
* Refactor duplicated code. NFC.Rafael Espindola2016-06-161-3/+5
| | | | llvm-svn: 272901
* Pass DebugLoc and SDLoc by const ref.Benjamin Kramer2016-06-121-61/+50
| | | | | | | | This used to be free, copying and moving DebugLocs became expensive after the metadata rewrite. Passing by reference eliminates a ton of track/untrack operations. No functionality change intended. llvm-svn: 272512
* Avoid copies of std::strings and APInt/APFloats where we only read from itBenjamin Kramer2016-06-081-2/+2
| | | | | | | | As suggested by clang-tidy's performance-unnecessary-copy-initialization. This can easily hit lifetime issues, so I audited every change and ran the tests under asan, which came back clean. llvm-svn: 272126
* ARM: correct TLS access on WoASaleem Abdulrasool2016-06-071-2/+12
| | | | | | | | | | | | TLS access requires an offset from the TLS index. The index itself is the section-relative distance of the symbol. For ARM, the relevant relocation (IMAGE_REL_ARM_SECREL) is applied as a constant. This means that the value may not be an immediate and must be lowered into a constant pool. This offset will not be base relocated. We were previously emitting the actual address of the symbol which would be base relocated and would therefore be the vaue offset by the ImageBase + TLS Offset. llvm-svn: 271974
* RAS extensions are part of ARMv8.2-A. This change enables them by introducing aSjoerd Meijer2016-06-031-1/+1
| | | | | | | | | | new instruction to ARM and AArch64 targets and several system registers. Patch by: Roger Ferrer Ibanez and Oliver Stannard Differential Revision: http://reviews.llvm.org/D20282 llvm-svn: 271670
* Avoid a load for local functions.Rafael Espindola2016-06-011-2/+7
| | | | llvm-svn: 271437
* Add a use of shouldAssumeDSOLocal to ARM.Rafael Espindola2016-05-311-2/+6
| | | | | | Now this code path knows about position independent executables. llvm-svn: 271290
* ARM: stop emitting blx instructions for most calls on MachO.Tim Northover2016-05-101-2/+1
| | | | | | | | | | | I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
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