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authorSam Parker <sam.parker@arm.com>2016-07-25 10:11:00 +0000
committerSam Parker <sam.parker@arm.com>2016-07-25 10:11:00 +0000
commitd5ca0a65b5075cd7ac46aca89e1b1f905c72922a (patch)
tree82c5fb4516978ea05d1ac17074c626ccd9b00bd9 /llvm/lib/Target/ARM/ARMISelLowering.cpp
parent618975206e7bdac07f52e3955032477960d4548b (diff)
downloadbcm5719-llvm-d5ca0a65b5075cd7ac46aca89e1b1f905c72922a.tar.gz
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[ARM] Improve longMAC codegen test
Added thumb targets and dataflow checks to the longMAC test. Differential Revision: https://reviews.llvm.org/D22684 llvm-svn: 276629
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMISelLowering.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 387c5ebc468..de2c659a6cd 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -8954,7 +8954,8 @@ static SDValue AddCombineTo64bitUMAAL(SDNode *AddcNode,
// be combined into a UMLAL. The other pattern is AddcNode being combined
// into an UMLAL and then using another addc is handled in ISelDAGToDAG.
- if (!Subtarget->hasV6Ops())
+ if (!Subtarget->hasV6Ops() ||
+ (Subtarget->isThumb() && !Subtarget->hasThumb2()))
return AddCombineTo64bitMLAL(AddcNode, DCI, Subtarget);
SDNode *PrevAddc = nullptr;
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