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* First part of refactoring ARM addrmode2 (load/store) instructions to be moreJim Grosbach2010-10-261-2/+137
| | | | | | | | explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
* trailing whitespaceJim Grosbach2010-10-211-4/+4
| | | | llvm-svn: 117050
* Support alignment for NEON vld-lane and vst-lane instructions.Bob Wilson2010-10-191-0/+11
| | | | llvm-svn: 116776
* Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode.Jim Grosbach2010-10-071-7/+9
| | | | llvm-svn: 115890
* Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.Jim Grosbach2010-10-071-8/+10
| | | | llvm-svn: 115884
* Add specializations of addrmode2 that allow differentiating those formsJim Grosbach2010-09-291-9/+33
| | | | | | | | | which require the use of the shifter-operand. This will be used to split the ldr/str instructions such that those versions needing the shifter operand can get a different scheduling itenerary, as in some cases, the use of the shifter can cause different scheduling than the simpler forms. llvm-svn: 115066
* Add braces for legibility.Jim Grosbach2010-09-291-1/+2
| | | | llvm-svn: 115043
* Set alignment operand for NEON VST instructions.Bob Wilson2010-09-231-14/+22
| | | | llvm-svn: 114709
* Set alignment operand for NEON VLD instructions.Bob Wilson2010-09-231-0/+16
| | | | llvm-svn: 114696
* fix a long standing wart: all the ComplexPattern's were beingChris Lattner2010-09-211-53/+45
| | | | | | | | | | | passed the root of the match, even though only a few patterns actually needed this (one in X86, several in ARM [which should be refactored anyway], and some in CellSPU that I don't feel like detangling). Instead of requiring all ComplexPatterns to take the dead root, have targets opt into getting the root by putting SDNPWantRoot on the ComplexPattern. llvm-svn: 114471
* Fix QOpcode assignment to Opc.Eric Christopher2010-09-141-2/+2
| | | | llvm-svn: 113837
* Convert some VTBL and VTBX instructions to use pseudo instructions prior toBob Wilson2010-09-131-14/+7
| | | | | | | register allocation. Remove the NEONPreAllocPass, which is no longer needed. Yeah!! llvm-svn: 113818
* Switch all the NEON vld-lane and vst-lane instructions over to the newBob Wilson2010-09-131-171/+60
| | | | | | | pseudo-instruction approach. Change ARMExpandPseudoInsts to use a table to record all the NEON load/store information. llvm-svn: 113812
* remove some dead code. t2addrmode_imm8s4 is never used in a Chris Lattner2010-09-051-30/+0
| | | | | | pattern, so there is no need to define a matching function. llvm-svn: 113122
* Finish converting the rest of the NEON VLD instructions to use pseudo-Bob Wilson2010-09-031-93/+52
| | | | | | | | | instructions prior to regalloc. Since it's getting a little close to the 2.8 branch deadline, I'll have to leave the rest of the instructions handled by the NEONPreAllocPass for now, but I didn't want to leave half of the VLD instructions converted and the other half not. llvm-svn: 112983
* Convert VLD1 and VLD2 instructions to use pseudo-instructions untilBob Wilson2010-09-021-35/+46
| | | | | | after regalloc. llvm-svn: 112825
* temporarily revert r112664, it is causing a decoding conflict, and Chris Lattner2010-09-011-97/+0
| | | | | | the testcases should be merged. llvm-svn: 112711
* We have a chance for an optimization. Consider this code:Bill Wendling2010-08-311-0/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | int x(int t) { if (t & 256) return -26; return 0; } We generate this: tst.w r0, #256 mvn r0, #25 it eq moveq r0, #0 while gcc generates this: ands r0, r0, #256 it ne mvnne r0, #25 bx lr Scandalous really! During ISel time, we can look for this particular pattern. One where we have a "MOVCC" that uses the flag off of a CMPZ that itself is comparing an AND instruction to 0. Something like this (greatly simplified): %r0 = ISD::AND ... ARMISD::CMPZ %r0, 0 @ sets [CPSR] %r0 = ARMISD::MOVCC 0, -26 @ reads [CPSR] All we have to do is convert the "ISD::AND" into an "ARM::ANDS" that sets [CPSR] when it's zero. The zero value will all ready be in the %r0 register and we only need to change it if the AND wasn't zero. Easy! llvm-svn: 112664
* Use pseudo instructions for VST1 and VST2.Bob Wilson2010-08-281-97/+33
| | | | llvm-svn: 112357
* We don't need to custom-select VLDMQ and VSTMQ anymore.Bob Wilson2010-08-281-38/+1
| | | | llvm-svn: 112336
* Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just likeBob Wilson2010-08-271-8/+8
| | | | | | | | | | | | | | | | | | | all the other LDM/STM instructions. This fixes asm printer crashes when compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run with -O0 to check this in the future. Prior to this change VLDM/VSTM used addressing mode #5, but not really. The offset field was used to hold a count of the number of registers being loaded or stored, and the AM5 opcode field was expanded to specify the IA or DB mode, instead of the standard ADD/SUB specifier. Much of the backend was not aware of these special cases. The crashes occured when rewriting a frameindex caused the AM5 offset field to be changed so that it did not have a valid submode. I don't know exactly what changed to expose this now. Maybe we've never done much with -O0 and NEON. Regardless, there's no longer any reason to keep a count of the VLDM/VSTM registers, so we can use addressing mode #4 and clean things up in a lot of places. llvm-svn: 112322
* Use pseudo instructions for VST3.Bob Wilson2010-08-261-9/+9
| | | | llvm-svn: 112208
* Use pseudo instructions for VST1d64Q.Bob Wilson2010-08-261-3/+2
| | | | llvm-svn: 112170
* Start converting NEON load/stores to use pseudo instructions, beginning hereBob Wilson2010-08-251-13/+31
| | | | | | | | | | | with the VST4 instructions. Until after register allocation, we want to represent sets of adjacent registers by a single super-register. These VST4 pseudo instructions have a single QQ or QQQQ source register operand. They get expanded to the real VST4 instructions with 4 separate D register operands. Once this conversion is complete, we'll be able to remove the NEONPreAllocPass and avoid some fragile and hacky code elsewhere. llvm-svn: 112108
* Don't call tablegen'ed Predicate_* functions in the ARM target.Jakob Stoklund Olesen2010-08-171-3/+13
| | | | llvm-svn: 111277
* Add -disable-shifter-op to disable isel of shifter ops. On Cortex-a9 the ↵Evan Cheng2010-07-301-0/+11
| | | | | | shifts cost extra instructions so it might be better to emit them separately to take advantage of dual-issues. llvm-svn: 109934
* Also use REG_SEQUENCE for VTBX instructions.Bob Wilson2010-07-071-15/+26
| | | | llvm-svn: 107743
* Use REG_SEQUENCE nodes to make the table registers for VTBL instructions beBob Wilson2010-07-061-1/+58
| | | | | | allocated to consecutive registers. llvm-svn: 107730
* Remove an unused and a pointless variable.Duncan Sands2010-06-291-3/+0
| | | | llvm-svn: 107131
* Eliminate unnecessary uses of getZExtValue().Dan Gohman2010-06-181-1/+1
| | | | llvm-svn: 106279
* Remove the hidden "neon-reg-sequence" option. The reg sequences are workingBob Wilson2010-06-161-262/+155
| | | | | | now, so there's no need to disable them. llvm-svn: 106155
* For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs andBob Wilson2010-06-041-12/+52
| | | | | | | | | | | VECTOR_SHUFFLEs to REG_SEQUENCE instructions. The standard ISD::BUILD_VECTOR node corresponds closely to REG_SEQUENCE but I couldn't use it here because its operands do not get legalized. That is pretty awful, but I guess it makes sense for other targets. Instead, I have added an ARM-specific version of BUILD_VECTOR that will have its operands properly legalized. This fixes the rest of Radar 7872877. llvm-svn: 105439
* Early implementation of tail call for ARM.Dale Johannesen2010-06-031-0/+1
| | | | | | | | | A temporary flag -arm-tail-calls defaults to off, so there is no functional change by default. Intrepid users may try this; simple cases work but there are bugs. llvm-svn: 105413
* Clean up 80 column violations. No functional change.Jim Grosbach2010-06-021-6/+8
| | | | llvm-svn: 105350
* Add the cc_out operand for t2RSBrs instructions. I missed this when I changedBob Wilson2010-05-281-2/+2
| | | | | | | the instruction class for t2RSB to add that operand in svn r104582. Radar 8033757. llvm-svn: 104907
* Fix a few places that depended on the numeric value of subreg indices.Jakob Stoklund Olesen2010-05-241-0/+5
| | | | | | Add assertions in places that depend on consecutive indices. llvm-svn: 104510
* Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enumsJakob Stoklund Olesen2010-05-241-49/+49
| | | | | | from ARMRegisterInfo.h llvm-svn: 104508
* Target instruction selection should copy memoperands.Evan Cheng2010-05-191-3/+11
| | | | llvm-svn: 104110
* Turn on -neon-reg-sequence by default.Evan Cheng2010-05-171-1/+2
| | | | | | Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers! llvm-svn: 103960
* Model vst lane instructions with REG_SEQUENCE.Evan Cheng2010-05-161-7/+75
| | | | llvm-svn: 103898
* Model 128-bit vld lane with REG_SEQUENCE.Evan Cheng2010-05-151-19/+44
| | | | llvm-svn: 103868
* Model 64-bit lane vld with REG_SEQUENCE.Evan Cheng2010-05-151-6/+28
| | | | llvm-svn: 103851
* Model VST*_UPD and VST*oddUPD pair with REG_SEQUENCE.Evan Cheng2010-05-141-25/+68
| | | | llvm-svn: 103833
* Model VLD*_UPD and VLD*odd_UPD pair with REG_SEQUENCE.Evan Cheng2010-05-141-16/+59
| | | | llvm-svn: 103790
* Fix comments.Evan Cheng2010-05-141-2/+2
| | | | llvm-svn: 103749
* Model some vst3 and vst4 with reg_sequence.Evan Cheng2010-05-111-5/+39
| | | | llvm-svn: 103453
* Model some vld3 instructions with REG_SEQUENCE.Evan Cheng2010-05-101-1/+34
| | | | llvm-svn: 103437
* Model vld2 / vst2 with reg_sequence.Evan Cheng2010-05-101-15/+84
| | | | llvm-svn: 103411
* Add a missing break statement to fix unintentional fall-throughBob Wilson2010-05-061-4/+3
| | | | | | (replacing the previous patch for the same issue). llvm-svn: 103183
* Fix unintentional fallthrough. Patch by Edmund Grimley-Evans ↵Jim Grosbach2010-05-061-1/+2
| | | | | | <Edmund.Grimley-Evans@arm.com> llvm-svn: 103181
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