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* Avoid an unused-variable warning when asserts are disabled.Kaelyn Uhrain2012-10-261-2/+1
| | | | llvm-svn: 166834
* 80 col.Jakob Stoklund Olesen2012-10-261-2/+4
| | | | llvm-svn: 166818
* Remove ARMBaseRegisterInfo::isReservedReg().Jakob Stoklund Olesen2012-10-261-16/+18
| | | | | | It is just as easy to use MRI::isReserved() now. llvm-svn: 166817
* Merge MRI::isPhysRegOrOverlapUsed() into isPhysRegUsed().Jakob Stoklund Olesen2012-10-171-2/+2
| | | | | | | | | | | All callers of these functions really want the isPhysRegOrOverlapUsed() functionality which also checks aliases. For historical reasons, targets without register aliases were calling isPhysRegUsed() instead. Change isPhysRegUsed() to also check aliases, and switch all isPhysRegOrOverlapUsed() callers to isPhysRegUsed(). llvm-svn: 166117
* Create enums for the different attributes.Bill Wendling2012-10-091-1/+1
| | | | | | | We use the enums to query whether an Attributes object has that attribute. The opaque layer is responsible for knowing where that specific attribute is stored. llvm-svn: 165488
* Remove the `hasFnAttr' method from Function.Bill Wendling2012-09-261-1/+1
| | | | | | | The hasFnAttr method has been replaced by querying the Attributes explicitly. No intended functionality change. llvm-svn: 164725
* Add support for the ARM GHC calling convention, this patch was in 3.0,Eric Christopher2012-08-031-0/+10
| | | | | | | | but somehow managed to be dropped later. Patch by Karel Gardas. llvm-svn: 161226
* Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-201-8/+8
| | | | | | since they are equivalent. llvm-svn: 155188
* Eliminate iOS-specific tail call instructions.Jakob Stoklund Olesen2012-04-061-13/+6
| | | | | | | After register masks were introdruced to represent the call clobbers, it is no longer necessary to have duplicate instruction for iOS. llvm-svn: 154209
* Remove some redundant checks.Bob Wilson2012-03-201-1/+1
| | | | | | | ARMFrameLowering::hasReservedCallFrame is already checking for variable sized objects, so there's no point in checking it twice. llvm-svn: 153109
* ARM refactor away a bunch of VLD/VST pseudo instructions.Jim Grosbach2012-03-051-5/+3
| | | | | | | | | With the new composite physical registers to represent arbitrary pairs of DPR registers, we don't need the pseudo-registers anymore. Get rid of a bunch of them that use DPR register pairs and just use the real instructions directly instead. llvm-svn: 152045
* Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper2012-03-041-4/+4
| | | | | | size of static data. llvm-svn: 151996
* Enable ARM base pointer when calling functions with large arguments.Jakob Stoklund Olesen2012-02-281-4/+7
| | | | | | | | | | | | | | | | | | When an outgoing call takes more than 2k of arguments on the stack, we don't allocate that call frame in the prolog, but adjust the stack pointer immediately before the call instead. This causes problems with the emergency spill slot because PEI can't track stack pointer adjustments on the second pass, and if the outgoing arguments are too big, SP can't be used to reach the emergency spill slot at all. Work around these problems by ensuring there is a base or frame pointer that can be used to access the emergency spill slot. <rdar://problem/10917166> llvm-svn: 151604
* Remove unused cl::opt, make another opt static.Benjamin Kramer2012-02-241-1/+1
| | | | llvm-svn: 151398
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Enable aligned NEON spilling by default.Jakob Stoklund Olesen2012-01-061-1/+1
| | | | | | Experiments show this to be a small speedup for modern ARM cores. llvm-svn: 147689
* Fix more places which should be checking for iOS, not darwin.Evan Cheng2012-01-041-10/+10
| | | | llvm-svn: 147513
* Fix Comments.Jakob Stoklund Olesen2011-12-241-3/+3
| | | | llvm-svn: 147238
* Experimental support for aligned NEON spills.Jakob Stoklund Olesen2011-12-231-11/+358
| | | | | | | | | | | | | ARM targets with NEON units have access to aligned vector loads and stores that are potentially faster than unaligned operations. Add support for spilling the callee-saved NEON registers to an aligned stack area using 16-byte aligned NEON loads and store. This feature is off by default, controlled by an -align-neon-spills command line option. llvm-svn: 147211
* Move common code into an MRI function.Jakob Stoklund Olesen2011-12-211-10/+1
| | | | llvm-svn: 147071
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-2/+1
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-021-1/+2
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :(Chad Rosier2011-10-201-4/+2
| | | | llvm-svn: 142557
* Add support for dynamic stack realignment when in thumb1 mode.Chad Rosier2011-10-181-2/+4
| | | | | | rdar://10288916 llvm-svn: 142337
* Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions."Chad Rosier2011-10-011-4/+2
| | | | | | to appease nightly testers. Not quite there yet. llvm-svn: 140953
* Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact Chad Rosier2011-10-011-2/+4
| | | | | | | | useful if an optimization assumes the stack has been realigned. Credit to Eli for his assistance. rdar://10043857 llvm-svn: 140924
* Thumb unconditional branches are allowed in IT blocks, and therefore should ↵Owen Anderson2011-09-091-0/+3
| | | | | | have a predicate operand, unlike conditional branches. llvm-svn: 139415
* Tidy up. Formatting.Jim Grosbach2011-09-021-2/+3
| | | | llvm-svn: 139024
* ARM fix for missing implicit operands on ldmia_ret.Andrew Trick2011-08-251-1/+3
| | | | | | rdar://10005094: miscompile of 176.gcc llvm-svn: 138568
* whitespaceAndrew Trick2011-08-251-1/+1
| | | | llvm-svn: 138566
* ARM refactor indexed store instructions.Jim Grosbach2011-08-051-8/+2
| | | | | | | | | | Refactor STR[B] pre and post indexed instructions to use addressing modes for memory operands, which is necessary for assembly parsing and is more consistent with the rest of the memory instruction definitions. Make some incremental progress on refactoring away the mega-operand addrmode2 along the way, which is nice. llvm-svn: 136978
* Split am2offset into register addend and immediate addend forms, necessary ↵Owen Anderson2011-07-261-5/+6
| | | | | | for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. llvm-svn: 136141
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng2011-07-201-1/+1
| | | | | | ARM MC code from target. llvm-svn: 135636
* ARM estimateStackSize() needs to account for simplified call frames.Jim Grosbach2011-07-051-7/+39
| | | | | | | | | | | | If the function allocates reserved stack space for callee argument frames, estimateStackSize() needs to account for that, as it doesn't show up as ordinary frame objects. Otherwise, a callee with a large argument list will throw off the calculations for whether to allocate an emergency spill slot and we get assert() failures in the register scavenger. rdar://9715469 llvm-svn: 134415
* Refact ARM Thumb1 tMOVr instruction family.Jim Grosbach2011-06-301-5/+5
| | | | | | | | | | Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions into tMOVr. There's no need to keep them separate. Giving the tMOVr instruction the proper GPR register class for its operands is sufficient to give the register allocator enough information to do the right thing directly. llvm-svn: 134204
* Thumb1 register to register MOV instruction is predicable.Jim Grosbach2011-06-301-11/+13
| | | | | | | | | Fix a FIXME and allow predication (in Thumb2) for the T1 register to register MOV instructions. This allows some better codegen with if-conversion (as seen in the test updates), plus it lays the groundwork for pseudo-izing the tMOVCC instructions. llvm-svn: 134197
* Update an insertion point iterator after replacing a return instruction with aCameron Zwarich2011-06-171-0/+1
| | | | | | tail call pseudoinstruction. This fixes <rdar://problem/9624333>. llvm-svn: 133227
* Fix coordination for using R4 in Thumb1 as a scratch for SP restore.Jim Grosbach2011-06-131-2/+7
| | | | | | | | The logic for reserving R4 for use as a scratch needs to match that for actually using it. Also, it's not necessary for immediate <=508, so adjust the value checked. llvm-svn: 132934
* In Thumb2 mode, lower frame indix references to:Evan Cheng2011-04-221-8/+11
| | | | | | | | | | | add <rd>, sp, #<imm8> ldr <rd>, [sp, #<imm8>] When the offset from sp is multiple of 4 and in range of 0-1020. This saves code size by utilizing 16-bit instructions. rdar://9321541 llvm-svn: 129971
* Clean up ARM tail calls a bit. They're pseudo-instructions for normal branches.Jim Grosbach2011-03-151-4/+6
| | | | | | | Also more cleanly separate the ARM vs. Thumb functionality. Previously, the encoding would be incorrect for some Thumb instructions (the indirect calls). llvm-svn: 127637
* Preliminary support for ARM frame save directives emission via MI flags.Anton Korobeynikov2011-03-051-14/+22
| | | | | | | This is just very first approximation how the stuff should be done (e.g. ARM-only for now). More to follow. llvm-svn: 127101
* Fix typo.Evan Cheng2011-02-251-1/+1
| | | | llvm-svn: 126467
* Each prologue may have multiple vpush instructions to store callee-savedEvan Cheng2011-02-251-2/+14
| | | | | | | | | | | D registers since the vpush list may not have gaps. Make sure the stack adjustment instruction isn't moved between them. Ditto for vpop in epilogues. Sorry, can't reduce a small test case. rdar://9043312 llvm-svn: 126457
* Remove unused bitvectors that record ARM callee-saved registers.Bob Wilson2011-02-141-6/+0
| | | | llvm-svn: 125534
* Don't merge restore with tail call instruction.Evan Cheng2011-01-251-1/+6
| | | | llvm-svn: 124167
* Remove unused variables found by gcc-4.6's -Wunused-but-set-variable.Jeffrey Yasskin2011-01-181-2/+0
| | | | llvm-svn: 123707
* Spill R4 if it's going to be used to restore SP from FP.Evan Cheng2011-01-161-4/+12
| | | | llvm-svn: 123567
* Teach frame lowering to ignore debug values after the terminators.Jakob Stoklund Olesen2011-01-131-2/+2
| | | | llvm-svn: 123399
* Tidy comments, indentation, and 80-column violations.Bob Wilson2011-01-131-37/+39
| | | | llvm-svn: 123397
* Clean up ARM subtarget code by using Triple ADT.Evan Cheng2011-01-111-0/+1
| | | | llvm-svn: 123276
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