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path: root/llvm/lib/Target/ARM/ARMFastISel.cpp
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* Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-201-12/+15
| | | | | | since they are equivalent. llvm-svn: 155188
* Tidy up. 80 columns.Jim Grosbach2012-04-061-1/+2
| | | | llvm-svn: 154226
* Deduplicate ARM call-related instructions.Jakob Stoklund Olesen2012-04-061-9/+4
| | | | | | | | We had special instructions for iOS because r9 is call-clobbered, but that is represented dynamically by the register mask operands now, so there is no need for the pseudo-instructions. llvm-svn: 154144
* Remove unnecessary llvm:: qualificationsCraig Topper2012-03-271-1/+1
| | | | llvm-svn: 153500
* Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.hCraig Topper2012-03-261-1/+0
| | | | llvm-svn: 153422
* Check if we can handle the arguments of a call (and therefore the call) inBill Wendling2012-03-161-8/+52
| | | | | | | | | | fast-isel before emitting code. If the program bails after code was emitted, then it could lead to the stack being adjusted more than once (two CALLSEQ_BEGINs emitted) but being adjuste back only once after the call. This leads to general badness and gnashing of teeth. <rdar://problem/11050630> llvm-svn: 152959
* [fast-isel] Address Eli's comments for r152847. Specifically, add a test caseChad Rosier2012-03-151-9/+8
| | | | | | | and still allow immediate encoding, just not with cmn. rdar://11038907 llvm-svn: 152869
* [fast-isel] Don't try to encode LONG_MIN using cmn instructions.Chad Rosier2012-03-151-5/+9
| | | | | | rdar://11038907 llvm-svn: 152847
* [fast-isel] ARMEmitCmp generates FMSTAT, which transfers the floating-point Chad Rosier2012-03-071-4/+2
| | | | | | | condition flags to CPSR. This allows us to simplify SelectCmp. Patch by Zonr Chang <zonr.xchg@gmail.com>. llvm-svn: 152243
* Split fpscr into two registers: FPSCR and FPSCR_NZCV.Lang Hames2012-03-061-1/+1
| | | | | | | | | The fpscr register contains both flags (set by FP operations/comparisons) and control bits. The control bits (FPSCR) should be reserved, since they're always available and needn't be defined before use. The flag bits (FPSCR_NZCV) should like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165. llvm-svn: 152076
* ARM use the right opcode for FP<->Integer move in fast-isel.Jim Grosbach2012-03-011-2/+2
| | | | | | rdar://10965031 llvm-svn: 151850
* Switch ARM target to register masks.Jakob Stoklund Olesen2012-02-241-0/+8
| | | | | | | | | | | | | I'll let the buildbots determine the compile time improvements from this change, but 464.h264ref has 5% faster codegen at -O2. This patch does cause some assembly changes. Branch folding can make different decisions about calls with dead return values. CriticalAntiDepBreaker may choose different registers because its liveness tracking is affected. MachineCopyPropagation may sometimes leave a dead copy behind. llvm-svn: 151331
* Make all pointers to TargetRegisterClass const since they are all pointers ↵Craig Topper2012-02-221-8/+8
| | | | | | to static data that should not be modified. llvm-svn: 151134
* [fast-isel] Add support for returning non-legal types with no sign- or zero-Chad Rosier2012-02-171-6/+6
| | | | | | entend flag. llvm-svn: 150774
* Remove unnecessary assignment to temporary, ResultReg.Chad Rosier2012-02-161-13/+8
| | | | llvm-svn: 150737
* Add braces to if clause to make symmetric with associate else clause.Chad Rosier2012-02-151-18/+19
| | | | llvm-svn: 150591
* Use a temporary variable, rather then a series of redundant calls.Chad Rosier2012-02-151-4/+5
| | | | llvm-svn: 150536
* Remove unnecessary assignment to temporary, ResultReg.Chad Rosier2012-02-141-8/+4
| | | | llvm-svn: 150520
* [fast-isel] Add support for SUBs with non-legal types.Chad Rosier2012-02-081-0/+5
| | | | llvm-svn: 150047
* [fast-isel] Add support for ORs with non-legal types.Chad Rosier2012-02-081-2/+13
| | | | llvm-svn: 150045
* [fast-isel] Add support for indirect branches.Chad Rosier2012-02-071-0/+13
| | | | llvm-svn: 150014
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-071-3/+1
| | | | llvm-svn: 149961
* [fast-isel] Add support for ADDs with non-legal types.Chad Rosier2012-02-061-5/+34
| | | | llvm-svn: 149934
* Persuade GCC that there is nothing worth warning about here (there isn't).Duncan Sands2012-02-051-0/+1
| | | | llvm-svn: 149834
* [fast-isel] Add support for URem.Chad Rosier2012-02-031-8/+10
| | | | llvm-svn: 149716
* [fast-isel] Rename isZExt to isSigned. No functional change intended.Chad Rosier2012-02-031-13/+14
| | | | llvm-svn: 149714
* [fast-isel] Add support for UDIV.Chad Rosier2012-02-031-8/+10
| | | | llvm-svn: 149712
* [fast-isel] Add support for FPToUI. Also add test cases for FPToSI.Chad Rosier2012-02-031-6/+8
| | | | llvm-svn: 149706
* [fast-isel] Add support for selecting UIToFP.Chad Rosier2012-02-031-6/+8
| | | | llvm-svn: 149704
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-1/+0
| | | | llvm-svn: 148578
* Fix assert.Eric Christopher2012-01-111-2/+2
| | | | llvm-svn: 147966
* Match SelectionDAG logic for enabling movt.Jakob Stoklund Olesen2012-01-071-1/+5
| | | | | | Darwin doesn't do static, and ELF targets only support static. llvm-svn: 147740
* Use getRegForValue() to materialize the address of ARM globals.Jakob Stoklund Olesen2012-01-071-10/+0
| | | | | | | | | This enables basic local CSE, giving us 20% smaller code for consumer-typeset in -O0 builds. <rdar://problem/10658692> llvm-svn: 147720
* Use movw+movt in ARMFastISel::ARMMaterializeGV.Jakob Stoklund Olesen2012-01-071-29/+50
| | | | | | | | | | | | | This eliminates a lot of constant pool entries for -O0 builds of code with many global variable accesses. This speeds up -O0 codegen of consumer-typeset by 2x because the constant island pass no longer has to look at thousands of constant pool entries. <rdar://problem/10629774> llvm-svn: 147712
* ARM target code clean up. Check for iOS, not Darwin where it makes sense.Evan Cheng2011-12-201-8/+8
| | | | llvm-svn: 146981
* VFP2 is required for FP loads. Noticed by inspection.Chad Rosier2011-12-141-0/+2
| | | | llvm-svn: 146569
* Tidy up.Chad Rosier2011-12-141-1/+2
| | | | llvm-svn: 146568
* Fix 80-column violation and extraneous brackets.Chad Rosier2011-12-141-8/+9
| | | | llvm-svn: 146566
* - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a functionEvan Cheng2011-12-141-2/+2
| | | | | | | | | | to finalize MI bundles (i.e. add BUNDLE instruction and computing register def and use lists of the BUNDLE instruction) and a pass to unpack bundles. - Teach more of MachineBasic and MachineInstr methods to be bundle aware. - Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to prevent IT blocks from being broken apart. llvm-svn: 146542
* [fast-isel] Unaligned loads of floats are not supported. Therefore, convert ↵Chad Rosier2011-12-131-7/+32
| | | | | | | | to a regular load and then move the result from a GPR to a FPR. llvm-svn: 146502
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-2/+1
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* [arm-fast-isel] Doublewords only require word-alignment.Chad Rosier2011-12-061-3/+4
| | | | | | rdar://10528060 llvm-svn: 145891
* Fix 80-column issues.Bob Wilson2011-12-041-4/+8
| | | | llvm-svn: 145783
* [arm-fast-isel] Unaligned stores of floats require special care.Chad Rosier2011-12-031-3/+18
| | | | | | rdar://10510150 llvm-svn: 145742
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-021-1/+1
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* [arm-fast-isel] After promoting a function parameter be sure to update theChad Rosier2011-12-021-2/+4
| | | | | | | | argument value type. Otherwise, the sign/zero-extend has no effect on arguments passed via the stack (i.e., undefined high-order bits). rdar://10515467 llvm-svn: 145701
* Silence wrong warnings from GCC about variables possibly being usedDuncan Sands2011-11-281-2/+2
| | | | | | | uninitialized: GCC doesn't understand that the variables are only used if !UseImm, in which case they have been initialized. llvm-svn: 145239
* Guard call to getRegForValue with isTypeLegal check to avoid unnecessary ↵Chad Rosier2011-11-181-3/+5
| | | | | | work/dead code. llvm-svn: 144959
* Add TODO comment.Chad Rosier2011-11-171-0/+2
| | | | llvm-svn: 144920
* Dead code.Chad Rosier2011-11-171-14/+0
| | | | llvm-svn: 144888
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