diff options
| author | Lang Hames <lhames@gmail.com> | 2012-03-06 00:19:55 +0000 |
|---|---|---|
| committer | Lang Hames <lhames@gmail.com> | 2012-03-06 00:19:55 +0000 |
| commit | 718cfbe05af42c55bb26f2feb03d84ddb9bf1cda (patch) | |
| tree | 779b95f7299ec1683a9582ee991782445e559bfe /llvm/lib/Target/ARM/ARMFastISel.cpp | |
| parent | b5e420f7072c937fb76b8e292a94eae454910e14 (diff) | |
| download | bcm5719-llvm-718cfbe05af42c55bb26f2feb03d84ddb9bf1cda.tar.gz bcm5719-llvm-718cfbe05af42c55bb26f2feb03d84ddb9bf1cda.zip | |
Split fpscr into two registers: FPSCR and FPSCR_NZCV.
The fpscr register contains both flags (set by FP operations/comparisons) and
control bits. The control bits (FPSCR) should be reserved, since they're always
available and needn't be defined before use. The flag bits (FPSCR_NZCV) should
like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165.
llvm-svn: 152076
Diffstat (limited to 'llvm/lib/Target/ARM/ARMFastISel.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMFastISel.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp index 818b20286af..365f1b66c8f 100644 --- a/llvm/lib/Target/ARM/ARMFastISel.cpp +++ b/llvm/lib/Target/ARM/ARMFastISel.cpp @@ -1496,7 +1496,7 @@ bool ARMFastISel::SelectCmp(const Instruction *I) { Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0); unsigned ZeroReg = TargetMaterializeConstant(Zero); bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy()); - unsigned CondReg = isFloat ? ARM::FPSCR : ARM::CPSR; + unsigned CondReg = isFloat ? ARM::FPSCR_NZCV : ARM::CPSR; BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg) .addReg(ZeroReg).addImm(1) .addImm(ARMPred).addReg(CondReg); |
