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* ARM: Implement big endian bit-conversion for NEON typeChristian Pirker2014-05-121-0/+2
| | | | llvm-svn: 208538
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-4/+5
| | | | llvm-svn: 207197
* FastISel: constrain the RegClass of operands when emitting instructions.Tim Northover2014-04-151-19/+0
| | | | | | | | | | | ARM64 suffered multiple -verify-machineinstr failures (principally over the xsp/xzr issue) because FastISel was completely ignoring which subset of the general-purpose registers each instruction required. More fixes are coming in ARM64 specific FastISel, but this should cover the generic problems. llvm-svn: 206283
* Tidy up. Trailing whitespace.Jim Grosbach2014-04-031-1/+1
| | | | llvm-svn: 205583
* remove a bunch of unused private methodsNuno Lopes2014-03-231-84/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | found with a smarter version of -Wunused-member-function that I'm playwing with. Appologies in advance if I removed someone's WIP code. include/llvm/CodeGen/MachineSSAUpdater.h | 1 include/llvm/IR/DebugInfo.h | 3 lib/CodeGen/MachineSSAUpdater.cpp | 10 -- lib/CodeGen/PostRASchedulerList.cpp | 1 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 10 -- lib/IR/DebugInfo.cpp | 12 -- lib/MC/MCAsmStreamer.cpp | 2 lib/Support/YAMLParser.cpp | 39 --------- lib/TableGen/TGParser.cpp | 16 --- lib/TableGen/TGParser.h | 1 lib/Target/AArch64/AArch64TargetTransformInfo.cpp | 9 -- lib/Target/ARM/ARMCodeEmitter.cpp | 12 -- lib/Target/ARM/ARMFastISel.cpp | 84 -------------------- lib/Target/Mips/MipsCodeEmitter.cpp | 11 -- lib/Target/Mips/MipsConstantIslandPass.cpp | 12 -- lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 21 ----- lib/Target/NVPTX/NVPTXISelDAGToDAG.h | 2 lib/Target/PowerPC/PPCFastISel.cpp | 1 lib/Transforms/Instrumentation/AddressSanitizer.cpp | 2 lib/Transforms/Instrumentation/BoundsChecking.cpp | 2 lib/Transforms/Instrumentation/MemorySanitizer.cpp | 1 lib/Transforms/Scalar/LoopIdiomRecognize.cpp | 8 - lib/Transforms/Scalar/SCCP.cpp | 1 utils/TableGen/CodeEmitterGen.cpp | 2 24 files changed, 2 insertions(+), 261 deletions(-) llvm-svn: 204560
* Prune includes in ARM target.Craig Topper2014-03-221-2/+3
| | | | llvm-svn: 204548
* [C++11] Mark the target fast isel classes as 'final' so that the compiler ↵Craig Topper2014-03-181-1/+1
| | | | | | can de-virtualize some of the internal calls. llvm-svn: 204123
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-101-6/+6
| | | | | | class. llvm-svn: 203433
* [Modules] Move CallSite into the IR library where it belogs. It isChandler Carruth2014-03-041-1/+1
| | | | | | | abstracting between a CallInst and an InvokeInst, both of which are IR concepts. llvm-svn: 202816
* [Modules] Move GetElementPtrTypeIterator into the IR library. As itsChandler Carruth2014-03-041-1/+1
| | | | | | | | | name might indicate, it is an iterator over the types in an instruction in the IR.... You see where this is going. Another step of modularizing the support library. llvm-svn: 202815
* Rename a DebugLoc variable to DbgLoc and a DataLayout to DL.Rafael Espindola2014-02-181-139/+157
| | | | | | This is quiet a bit less confusing now that TargetData was renamed DataLayout. llvm-svn: 201606
* ARM: fix fast-isel assertion failureTim Northover2014-02-041-1/+2
| | | | | | | | | Missing braces on if meant we inserted both ARM and Thumb load for a litpool entry. This didn't end well. rdar://problem/15959157 llvm-svn: 200752
* ARM MachO: sort out isTargetDarwin/isTargetIOS/... checks.Tim Northover2014-01-061-5/+5
| | | | | | | | | | | | | | | | | | The ARM backend has been using most of the MachO related subtarget checks almost interchangeably, and since the only target it's had to run on has been IOS (which is all three of MachO, Darwin and IOS) it's worked out OK so far. But we'd like to support embedded targets under the "*-*-none-macho" triple, which means everything starts falling apart and inconsistent behaviours emerge. This patch should pick a reasonably sensible set of behaviours for the new triple (and any others that come along, with luck). Some choices were debatable (notably FP == r7 or r11), but we can revisit those later when deficiencies become apparent. llvm-svn: 198617
* Keep comment with 'Subtarget' ivar.Bill Wendling2013-12-301-1/+1
| | | | llvm-svn: 198201
* Store the global variable that's created so that it's reclaimed afterwards.Bill Wendling2013-12-291-1/+3
| | | | | | | | This plugs a memory leak in ARM's FastISel by storing the GV in Module so that it's reclaimed. PR17978 llvm-svn: 198160
* ARM: constrain register-class in fast-iselTim Northover2013-12-111-1/+3
| | | | | | | | The tests were no longer using fast-isel at all (MachO needs an "ios" rather than "darwin" triple at the moment and Linux needs ARM mode). Once that was corrected, the verifier complained about a t2ADDri created for the alloca. llvm-svn: 197046
* Darwin-ARM: use movw/movt for static relocationsTim Northover2013-11-261-5/+3
| | | | llvm-svn: 195759
* ARM: remove special cases for Darwin dynamic-no-pic mode.Tim Northover2013-11-251-4/+5
| | | | | | | | | These are handled almost identically to static mode (and ELF's global address materialisation), except that a symbol may have "$non_lazy_ptr" appended. This can be handled by passing appropriate flags along with the instruction instead of using entirely separate pseudo-instructions. llvm-svn: 195655
* Avoid illegal integer promotion in fastiselBob Wilson2013-11-151-7/+2
| | | | | | | | | | | | | | | | | Stop folding constant adds into GEP when the type size doesn't match. Otherwise, the adds' operands are effectively being promoted, changing the conditions of an overflow. Results are different when: sext(a) + sext(b) != sext(a + b) Problem originally found on x86-64, but also fixed issues with ARM and PPC, which used similar code. <rdar://problem/15292280> Patch by Duncan Exon Smith! llvm-svn: 194840
* [ARMv8] Prevent generation of deprecated IT blocks on ARMv8 in Thumb mode.Joey Gouly2013-09-091-3/+3
| | | | | | | | | IT blocks can only be one instruction lonf, and can only contain a subset of the 16 instructions. Patch by Artyom Skrobov! llvm-svn: 190309
* ARM: Constrain regclass for TSTri instruction.Jim Grosbach2013-08-261-0/+2
| | | | | | | | | Get the register class right for the TST instruction. This keeps the machine verifier happy, enabling us to turn it on for another test. rdar://12594152 llvm-svn: 189274
* ARM: FastISel verifier error cleanup.Jim Grosbach2013-08-261-0/+7
| | | | | | | | | Constant pool and global value reference instructions need more restricted register classes than plain GPR. rdar://12594152 llvm-svn: 189270
* [ARM] Fix another ARM FastISel -verify-machineinstrs issue.Joey Gouly2013-08-231-0/+4
| | | | llvm-svn: 189109
* Fix ARM FastISel PIC function call.Logan Chien2013-08-221-2/+9
| | | | | | | The function call to external function should come with PLT relocation type if the PIC relocation model is used. llvm-svn: 189002
* ARM: Fix fast-isel copy/paste-o.Jim Grosbach2013-08-201-1/+1
| | | | | | | | | | | | Update testcase to be more careful about checking register values. While regexes are general goodness for these sorts of testcases, in this example, the registers are constrained by the calling convention, so we can and should check their explicit values. rdar://14779513 llvm-svn: 188819
* ARM: Properly constrain comparison fastisel register classes.Jim Grosbach2013-08-161-5/+12
| | | | | | | | Ongoing 'make the verifier happy' improvements to ARM fast-isel. rdar://12594152 llvm-svn: 188595
* ARM: Fast-isel register class constrain for extends.Jim Grosbach2013-08-161-0/+1
| | | | | | | | | | Properly constrain the operand register class for instructions used in [sz]ext expansion. Update more tests to use the verifier now that we're getting the register classes correct. rdar://12594152 llvm-svn: 188594
* ARM: Fix more fast-isel verifier failures.Jim Grosbach2013-08-161-0/+43
| | | | | | | | | | | | | Teach the generic instruction selection helper functions to constrain the register classes of their input operands. For non-physical register references, the generic code needs to be careful not to mess that up when replacing references to result registers. As the comment indicates for MachineRegisterInfo::replaceRegWith(), it's important to call constrainRegClass() first. rdar://12594152 llvm-svn: 188593
* ARM: Clean up fast-isel machine verifier errors.Jim Grosbach2013-08-161-1/+1
| | | | | | | | | | | | | Lots of machine verifier errors result from using a plain GPR regclass for incoming argument copies. A more restrictive rGPR class is more appropriate since it more accurately represents what's happening, plus it lines up better with isel later on so the verifier is happier. Reduces the number of ARM fast-isel tests not running with the verifier enabled by over half. rdar://12594152 llvm-svn: 188592
* Replace getValueType().getSimpleVT() with getSimpleValueType(). Also remove ↵Craig Topper2013-08-151-1/+1
| | | | | | one weird cast from MVT->EVT just to call getSimpleVT(). llvm-svn: 188441
* Fix yet another memory leak found by the vg-leak bot. Folks (includingChandler Carruth2013-07-271-2/+6
| | | | | | | | | | | | | | | | me) should start watching this bot more as its catching lots of bugs. The fix here is to not construct the global if we aren't going to need it. That's cheaper anyways, and globals have highly predictable types in practice. I've added an assert to catch skew between our manual testing of the type and the actual type just for paranoia's sake. Note that this pattern is actually fine in most globals because when you build a global with a module it automatically is moved to be owned by that module. But here, we're in isel and don't really want to do that. The solution of not creating a global is simpler anyways. llvm-svn: 187302
* Fix ARMFastISel::ARMEmitIntExt shift emissionJF Bastien2013-07-171-30/+52
| | | | | | | | My patch 'r183551 - ARM FastISel integer sext/zext improvements' was incorrect when emitting ARM register-immediate ASR, LSL, LSR instructions: they are pseudo-instructions in ARMInstrInfo.td and I should have used MOVsi instead. This is not an issue when code is generated through a .s file, but is an issue when generated straight to a .o (-filetype=obj). llvm-svn: 186489
* Remove extraneous braces.Eric Christopher2013-07-121-6/+3
| | | | llvm-svn: 186212
* DebugInfo: Don't lose unreferenced non-trivial by-value parametersDavid Blaikie2013-06-211-2/+0
| | | | | | | | | | | | A FastISel optimization was causing us to emit no information for such parameters & when they go missing we end up emitting a different function type. By avoiding that shortcut we not only get types correct (very important) but also location information (handy) - even if it's only live at the start of a function & may be clobbered later. Reviewed/discussion by Evan Cheng & Dan Gohman. llvm-svn: 184604
* Enable FastISel on ARM for Linux and NaCl, not MCJITJF Bastien2013-06-141-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a resubmit of r182877, which was reverted because it broken MCJIT tests on ARM. The patch leaves MCJIT on ARM as it was before: only enabled for iOS. I've CC'ed people from the original review and revert. FastISel was only enabled for iOS ARM and Thumb2, this patch enables it for ARM (not Thumb2) on Linux and NaCl, but not MCJIT. Thumb2 support needs a bit more work, mainly around register class restrictions. The patch punts to SelectionDAG when doing TLS relocation on non-Darwin targets. I will fix this and other FastISel-to-SelectionDAG failures in a separate patch. The patch also forces FastISel to retain frame pointers: iOS always keeps them for backtracking (so emitted code won't change because of this), but Linux was getting much worse code that was incorrect when using big frames (such as test-suite's lencod). I'll also fix this in a later patch, it will probably require a peephole so that FastISel doesn't rematerialize frame pointers back-to-back. The test changes are straightforward, similar to: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html They also add a vararg test that got dropped in that change. I ran all of lnt test-suite on A15 hardware with --optimize-option=-O0 and all the tests pass. All the tests also pass on x86 make check-all. I also re-ran the check-all tests that failed on ARM, and they all seem to pass. llvm-svn: 183966
* ARM FastISel fix sext/zext foldJF Bastien2013-06-111-19/+36
| | | | | | | | | | | Sign- and zero-extension folding was slightly incorrect because it wasn't checking that the shift on extensions was zero. Further, I recently added AND rd, rn, #255 as a form of 8-bit zero extension, and failed to add the folding code for it. This patch fixes both issues. This patch fixes both, and the test should remain the same: test/CodeGen/ARM/fast-isel-fold.ll llvm-svn: 183794
* ARM FastISel fix load register classesJF Bastien2013-06-091-4/+4
| | | | | | | | The register classes when emitting loads weren't quite restricting enough, leading to MI verification failure on the result register. These are new failures that weren't there the first time I tried enabling ARM FastISel for new targets. llvm-svn: 183624
* Fix unused variable warning from my previous patch.JF Bastien2013-06-081-0/+1
| | | | llvm-svn: 183601
* ARM FastISel integer sext/zext improvementsJF Bastien2013-06-071-38/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | My recent ARM FastISel patch exposed this bug: http://llvm.org/bugs/show_bug.cgi?id=16178 The root cause is that it can't select integer sext/zext pre-ARMv6 and asserts out. The current integer sext/zext code doesn't handle other cases gracefully either, so this patch makes it handle all sext and zext from i1/i8/i16 to i8/i16/i32, with and without ARMv6, both in Thumb and ARM mode. This should fix the bug as well as make FastISel faster because it bails to SelectionDAG less often. See fastisel-ext.patch for this. fastisel-ext-tests.patch changes current tests to always use reg-imm AND for 8-bit zext instead of UXTB. This simplifies code since it is supported on ARMv4t and later, and at least on A15 both should perform exactly the same (both have exec 1 uop 1, type I). 2013-05-31-char-shift-crash.ll is a bitcode version of the above bug 16178 repro. fast-isel-ext.ll tests all sext/zext combinations that ARM FastISel should now handle. Note that my ARM FastISel enabling patch was reverted due to a separate failure when dealing with MCJIT, I'll fix this second failure and then turn FastISel on again for non-iOS ARM targets. I've tested "make check-all" on my x86 box, and "lnt test-suite" on A15 hardware. llvm-svn: 183551
* Revert r182937 and r182877.Rafael Espindola2013-05-301-17/+3
| | | | | | | | | r182877 broke MCJIT tests on ARM and r182937 was working around another failure by r182877. This should make the ARM bots green. llvm-svn: 182960
* Enable FastISel on ARM for Linux and NaClJF Bastien2013-05-291-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | FastISel was only enabled for iOS ARM and Thumb2, this patch enables it for ARM (not Thumb2) on Linux and NaCl. Thumb2 support needs a bit more work, mainly around register class restrictions. The patch punts to SelectionDAG when doing TLS relocation on non-Darwin targets. I will fix this and other FastISel-to-SelectionDAG failures in a separate patch. The patch also forces FastISel to retain frame pointers: iOS always keeps them for backtracking (so emitted code won't change because of this), but Linux was getting much worse code that was incorrect when using big frames (such as test-suite's lencod). I'll also fix this in a later patch, it will probably require a peephole so that FastISel doesn't rematerialize frame pointers back-to-back. The test changes are straightforward, similar to: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html They also add a vararg test that got dropped in that change. I ran all of test-suite on A15 hardware with --optimize-option=-O0 and all the tests pass. llvm-svn: 182877
* Tidy some register classes for ARM and ThumbJF Bastien2013-05-291-2/+2
| | | | | | | | | | | | | | | | | | Tidy up three places where the register class for ARM and Thumb wasn't restrictive enough: - No PC dest for reg-reg add/orr/sub. - No PC dest for shifts. - No PC or SP for Thumb2 reg-imm add. I encountered this while combining FastISel with -verify-machineinstrs. These instructions defined registers whose classes weren't restrictive enough, and the uses failed verification. They're also undefined in the ISA, or would produce code that FastISel wouldn't want. This doesn't fix the register class narrowing issue (where uses should restrict definitions), and isn't thorough, but it's a small step in the right direction. llvm-svn: 182863
* No really, don't store anything to this since it's unconditionallyEric Christopher2013-04-221-1/+1
| | | | | | set below. llvm-svn: 180015
* Remove variable store that is never read.Eric Christopher2013-04-221-1/+1
| | | | llvm-svn: 180014
* Move TryToFoldFastISelLoad to FastISel, where it belongs. In general, I'mEli Bendersky2013-04-191-5/+5
| | | | | | | trying to move as much FastISel logic as possible out of the main path in SelectionDAGISel - intermixing them just adds confusion. llvm-svn: 179902
* [fast-isel] Make sure the FastLowerArguments function checks to make sure theChad Rosier2013-02-261-0/+1
| | | | | | | arguments type is a simple type. rdar://13290455 llvm-svn: 176066
* [fast-isel] Remove an invalid assert.Chad Rosier2013-02-181-1/+0
| | | | | | | | If the memcpy has an odd length with an alignment of 2, this would incorrectly assert on the last 1 byte copy. rdar://13202135 llvm-svn: 175459
* Currently, codegen may spent some time in SDISel passes even if an entireEvan Cheng2013-02-111-0/+74
| | | | | | | | | | | | | | function is successfully handled by fast-isel. That's because function arguments are *always* handled by SDISel. Introduce FastLowerArguments to allow each target to provide hook to handle formal argument lowering. As a proof-of-concept, add ARMFastIsel::FastLowerArguments to handle functions with 4 or fewer scalar integer (i8, i16, or i32) arguments. It completely eliminates the need for SDISel for trivial functions. rdar://13163905 llvm-svn: 174855
* Move MRI liveouts to ARM return instructions.Jakob Stoklund Olesen2013-02-051-4/+10
| | | | llvm-svn: 174406
* Add a special ARM trap encoding for NaCl.Eli Bendersky2013-01-301-1/+2
| | | | | | | | More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html Patch by JF Bastien llvm-svn: 173943
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