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authorEric Christopher <echristo@gmail.com>2013-04-22 13:51:44 +0000
committerEric Christopher <echristo@gmail.com>2013-04-22 13:51:44 +0000
commit6647fb2c60cb24a3cf624c16045dcd72f0be263a (patch)
treeff7cd2a4a270d7c8b3a45a8b13f7f90f0c29f9c3 /llvm/lib/Target/ARM/ARMFastISel.cpp
parent845c2ca78c9f16ee19a9fd789e8fce335ada3009 (diff)
downloadbcm5719-llvm-6647fb2c60cb24a3cf624c16045dcd72f0be263a.tar.gz
bcm5719-llvm-6647fb2c60cb24a3cf624c16045dcd72f0be263a.zip
Remove variable store that is never read.
llvm-svn: 180014
Diffstat (limited to 'llvm/lib/Target/ARM/ARMFastISel.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMFastISel.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp
index c5b9e50e0c0..c678e8eaf07 100644
--- a/llvm/lib/Target/ARM/ARMFastISel.cpp
+++ b/llvm/lib/Target/ARM/ARMFastISel.cpp
@@ -2605,7 +2605,7 @@ unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
unsigned Opc;
bool isBoolZext = false;
- const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::i32);
+ const TargetRegisterClass *RC = 0;
switch (SrcVT.SimpleTy) {
default: return 0;
case MVT::i16:
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