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path: root/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
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* Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 ↵Owen Anderson2011-02-081-38/+5
| | | | | | (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. llvm-svn: 125127
* Change VLD3/4 and VST3/4 for quad registers to not update the address register.Bob Wilson2011-02-071-1/+25
| | | | | | | | | | | | These operations are expanded to pairs of loads or stores, and the first one uses the address register update to produce the address for the second one. So far, the second load/store has also updated the address register, just for convenience, since that output has never been used. In anticipation of actually supporting post-increment updates for these operations, this changes the non-updating operations to use a non-updating load/store for the second instruction. llvm-svn: 125013
* Null initialize a few variables flagged byTed Kremenek2011-01-231-1/+1
| | | | | | | | | | clang's -Wuninitialized-experimental warning. While these don't look like real bugs, clang's -Wuninitialized-experimental analysis is stricter than GCC's, and these fixes have the benefit of being general nice cleanups. llvm-svn: 124073
* Last round of fixes for movw + movt global address codegen.Evan Cheng2011-01-211-20/+33
| | | | | | | | | | 1. Fixed ARM pc adjustment. 2. Fixed dynamic-no-pic codegen 3. CSE of pc-relative load of global addresses. It's now enabled by default for Darwin. llvm-svn: 123991
* Sorry, several patches in one.Evan Cheng2011-01-201-141/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. llvm-svn: 123905
* Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.Evan Cheng2011-01-171-10/+37
| | | | | | | | | | | | movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4)) movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4)) LPC0_0: add r0, pc, r0 It's not yet enabled by default as some tests are failing. I suspect bugs in down stream tools. llvm-svn: 123619
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov2011-01-101-2/+2
| | | | | | and fixes here and there. llvm-svn: 123170
* Revert r121721, which broke buildbots.Owen Anderson2010-12-131-15/+0
| | | | llvm-svn: 121726
* Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. ↵Owen Anderson2010-12-131-0/+15
| | | | | | | | Provide correct fixups for Thumb2 ADR, which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup. llvm-svn: 121721
* Use COPY_TO_REGCLASS instead of pseudo instructions for Neon FP patterns.Bob Wilson2010-12-131-23/+0
| | | | | | | | Jakob Olesen suggested that we can avoid the need for separate pseudo instructions here by using COPY_TO_REGCLASS in the patterns. The pattern gets pretty ugly but it seems to work well. Partial fix for Radar 8711675. llvm-svn: 121718
* Use pseudo instructions for 2-register Neon instructions for scalar FP.Bob Wilson2010-12-131-12/+29
| | | | | | Partial fix for Radar 8711675. llvm-svn: 121716
* Remove unused variablesMatt Beaumont-Gay2010-12-091-2/+0
| | | | llvm-svn: 121343
* Remove extraneous semicolon.Bill Wendling2010-12-091-1/+1
| | | | llvm-svn: 121338
* Style nit and whitespace cleanupJason W Kim2010-12-081-2/+2
| | | | llvm-svn: 121317
* Removed dead comment.Jason W Kim2010-12-081-2/+0
| | | | llvm-svn: 121313
* ARM/MC/ELF TPsoft is now a proper pseudo inst.Jason W Kim2010-12-081-0/+15
| | | | | | | | | Added test to check bl __aeabi_read_tp gets emitted properly for ELF/ASM as well as ELF/OBJ (including fixup) Also added support for ELF::R_ARM_TLS_IE32 llvm-svn: 121312
* Second attempt at converting Thumb2's LDRpci, including updating the ↵Owen Anderson2010-12-071-4/+36
| | | | | | gazillion places that need to know about it. llvm-svn: 121082
* Revert r121021, which broke the buildbots.Owen Anderson2010-12-061-32/+2
| | | | llvm-svn: 121026
* Trailing whitespace.Jim Grosbach2010-12-061-1/+1
| | | | llvm-svn: 121024
* Improve handling of Thumb2 PC-relative loads by converting LDRpci (and ↵Owen Anderson2010-12-061-2/+32
| | | | | | friends) to Pseudos. llvm-svn: 121021
* When expanding the MOVCCi32imm, make sure to use the ARM movt/movw opcodes,Jim Grosbach2010-12-021-4/+5
| | | | | | not thumb2. llvm-svn: 120711
* Add support for NEON VLD3-dup instructions.Bob Wilson2010-11-301-0/+13
| | | | | | The encoding for alignment in VLD4-dup instructions is still a work in progress. llvm-svn: 120356
* Add support for NEON VLD3-dup instructions.Bob Wilson2010-11-291-0/+13
| | | | llvm-svn: 120312
* Add support for NEON VLD2-dup instructions.Bob Wilson2010-11-281-0/+13
| | | | llvm-svn: 120236
* Add NEON VLD1-dup instructions (load 1 element to all lanes).Bob Wilson2010-11-271-0/+13
| | | | llvm-svn: 120194
* Avoid release build warnings.Benjamin Kramer2010-11-191-2/+2
| | | | llvm-svn: 119804
* Move hasFP() and few related hooks to TargetFrameInfo.Anton Korobeynikov2010-11-181-1/+3
| | | | llvm-svn: 119740
* Encode the multi-load/store instructions with their respective modes ('ia',Bill Wendling2010-11-161-8/+21
| | | | | | | | | 'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> llvm-svn: 119310
* Add conditional move of large immediate.Evan Cheng2010-11-131-3/+7
| | | | llvm-svn: 118968
* Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either ↵Evan Cheng2010-11-121-28/+24
| | | | | | movi+orr or movw+movt depending on the subtarget. llvm-svn: 118938
* Add NEON VST1-lane instructions. Partial fix for Radar 8599955.Bob Wilson2010-11-021-3/+16
| | | | llvm-svn: 118069
* Add NEON VLD1-lane instructions. Partial fix for Radar 8599955.Bob Wilson2010-11-011-3/+19
| | | | llvm-svn: 117964
* Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it inJim Grosbach2010-10-291-0/+28
| | | | | | the ARMExpandPseudos pass rather than during the asm lowering. llvm-svn: 117714
* Switch attribute macros to use 'LLVM_' as a prefix. We retain the old namesChandler Carruth2010-10-231-2/+2
| | | | | | until other LLVM projects using these are cleaned up. llvm-svn: 117200
* The return value of this call is not used, so no pointDuncan Sands2010-10-211-8/+7
| | | | | | in assigning it to a variable (gcc-4.6 warning). llvm-svn: 117024
* Fix backwards conditional.Jim Grosbach2010-10-201-1/+1
| | | | llvm-svn: 116897
* Add dynamic realignment when rematerializing the base register.Jim Grosbach2010-10-201-0/+13
| | | | llvm-svn: 116886
* Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do anyJim Grosbach2010-10-191-2/+38
| | | | | | | setup they require. Use this for ARM/Darwin to rematerialize the base pointer from the frame pointer when required. rdar://8564268 llvm-svn: 116879
* Use simple RegState::Define flag instead of getDefRegState(true).Bob Wilson2010-10-151-5/+5
| | | | llvm-svn: 116601
* When expanding the MOVsr[la]_flag pseudos, the CPSR implicit def becomesJim Grosbach2010-10-151-2/+1
| | | | | | an explicit def. Make sure to capture that properly. rdar://8556556 llvm-svn: 116591
* Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudosJim Grosbach2010-10-141-0/+29
| | | | | | | and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs) instruction form. llvm-svn: 116534
* Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually beJim Grosbach2010-10-061-0/+26
| | | | | | pseudo instructions. llvm-svn: 115840
* When expanding ARM pseudo registers, copy the existing predicate operandsBob Wilson2010-09-161-9/+29
| | | | | | instead of using default predicates on the expanded instructions. llvm-svn: 114066
* Add missing break.Bob Wilson2010-09-161-0/+1
| | | | llvm-svn: 114048
* Change VLDMQ and VSTMQ to be pseudo instructions. They are expanded afterBob Wilson2010-09-161-0/+50
| | | | | | | register allocation to VLDMD and VSTMD respectively. This avoids using the dregpair operand modifier. llvm-svn: 114047
* Avoid warnings.Bob Wilson2010-09-141-2/+3
| | | | llvm-svn: 113857
* Convert some VTBL and VTBX instructions to use pseudo instructions prior toBob Wilson2010-09-131-3/+54
| | | | | | | register allocation. Remove the NEONPreAllocPass, which is no longer needed. Yeah!! llvm-svn: 113818
* Switch all the NEON vld-lane and vst-lane instructions over to the newBob Wilson2010-09-131-160/+435
| | | | | | | pseudo-instruction approach. Change ARMExpandPseudoInsts to use a table to record all the NEON load/store information. llvm-svn: 113812
* For double-spaced VLD3/VLD4 instructions, copy the explicit super-register useBob Wilson2010-09-091-5/+9
| | | | | | | operand from the pseudo instruction to the new instruction as an implicit use. This will preserve any other flags (e.g., kill) on the operand. llvm-svn: 113456
* Simplify copying over operands from pseudo NEON load/store instructions.Bob Wilson2010-09-091-30/+19
| | | | | | | | For VLD3/VLD4 with double-spaced registers, add the implicit use of the super register for both the instruction loading the even registers and the instruction loading the odd registers. llvm-svn: 113452
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