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path: root/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
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* Fix buglet when the TST instruction directly uses the AND result.Gabor Greif2010-09-211-5/+6
| | | | | | | I am unable to write a test for this case, help is solicited, though... What I did is to tickle the code in the debugger and verify that we do the right thing. llvm-svn: 114430
* Move the search for the appropriate AND instructionGabor Greif2010-09-211-18/+42
| | | | | | | | | | into OptimizeCompareInstr. This necessitates the passing of CmpValue around, so widen the virtual functions to accomodate. No functionality changes. llvm-svn: 114428
* convert targets to the new MF.getMachineMemOperand interface.Chris Lattner2010-09-211-4/+6
| | | | llvm-svn: 114391
* Remember VLDMQ.Jakob Stoklund Olesen2010-09-151-0/+9
| | | | llvm-svn: 114026
* Add missing break.Jakob Stoklund Olesen2010-09-151-0/+1
| | | | llvm-svn: 114025
* Recognize VST1q64Pseudo and VSTMQ as stack slot stores.Jakob Stoklund Olesen2010-09-151-0/+22
| | | | | | | | | Recognize VLD1q64Pseudo as a stack slot load. Reject these if they are loading or storing a subregister. The API (and VirtRegRewriter) doesn't know how to deal with that. llvm-svn: 113985
* Reapply Gabor's 113839, 113840, and 113876 with a fix for a problemBob Wilson2010-09-151-0/+17
| | | | | | | | encountered while building llvm-gcc for arm. This is probably the same issue that the ppc buildbot hit. llvm::prior works on a MachineBasicBlock::iterator, not a plain MachineInstr. llvm-svn: 113983
* the darwin9-powerpc buildbot keeps consistently crashing,Gabor Greif2010-09-151-16/+0
| | | | | | | | | | backing out following to get it back to green, so I can investigate in peace: svn merge -c -113840 llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll svn merge -c -113876 -c -113839 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm-svn: 113980
* Move ARM is{LoadFrom,StoreTo}StackSlot closer to their siblings so they won't beJakob Stoklund Olesen2010-09-151-78/+64
| | | | | | | | | | forgotten in the future. Coalesce identical cases in switch. No functional changes intended. llvm-svn: 113979
* Spelling fix.Bob Wilson2010-09-151-1/+1
| | | | llvm-svn: 113978
* Use VLD1/VST1 pseudo instructions for loadRegFromStackSlot andBob Wilson2010-09-151-15/+9
| | | | | | storeRegToStackSlot. llvm-svn: 113918
* an attempt to salvage the darwin9-powerpc buildbot, which could be ↵Gabor Greif2010-09-141-1/+2
| | | | | | miscompiling this line llvm-svn: 113876
* Eliminate a 'tst' that immediately follows an 'and'Gabor Greif2010-09-141-0/+15
| | | | | | | | | | | | | | | | by morphing the 'and' to its recording form 'andS'. This is basically a test commit into this area, to see whether the bots like me. Several generalizations can be applied and various avenues of code simplification are open. I'll introduce those as I go. I am aware of stylistic input from Bill Wendling, about where put the analysis complexity, but I am positive that we can move things around easily and will find a satisfactory solution. llvm-svn: 113839
* Rename ConvertToSetZeroFlag to something more general.Bill Wendling2010-09-111-2/+2
| | | | llvm-svn: 113670
* No need to recompute the SrcReg and CmpValue.Bill Wendling2010-09-101-4/+2
| | | | llvm-svn: 113666
* Move some of the decision logic for converting an instruction into one that setsBill Wendling2010-09-101-4/+17
| | | | | | | the 'zero' bit down into the back-end. There are other cases where this logic isn't sufficient, so they should be handled separately. llvm-svn: 113665
* Modify the comparison optimizations in the peephole optimizer to update theBill Wendling2010-09-101-2/+5
| | | | | | | iterator when an optimization took place. This allows us to do more insane things with the code than just remove an instruction or two. llvm-svn: 113640
* Add a missing case to duplicateCPV() for LSDA constants. Add a FIXME. ↵Jim Grosbach2010-09-101-0/+8
| | | | | | rdar://8302157 llvm-svn: 113637
* Teach if-converter to be more careful with predicating instructions that wouldEvan Cheng2010-09-101-12/+28
| | | | | | | | | | | take multiple cycles to decode. For the current if-converter clients (actually only ARM), the instructions that are predicated on false are not nops. They would still take machine cycles to decode. Micro-coded instructions such as LDM / STM can potentially take multiple cycles to decode. If-converter should take treat them as non-micro-coded simple instructions. llvm-svn: 113570
* For each instruction itinerary class, specify the number of micro-ops eachEvan Cheng2010-09-091-0/+63
| | | | | | | | | | instruction in the class would be decoded to. Or zero if the number of uOPs must be determined dynamically. This will be used to determine the cost-effectiveness of predicating a micro-coded instruction. llvm-svn: 113513
* remove obsolete commentJim Grosbach2010-09-081-1/+0
| | | | llvm-svn: 113337
* correct spill code to properly determine if dynamic stack realignment isJim Grosbach2010-09-081-2/+2
| | | | | | | present in the function and thus whether aligned load/store instructions can be used. llvm-svn: 113323
* Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just likeBob Wilson2010-08-271-6/+6
| | | | | | | | | | | | | | | | | | | all the other LDM/STM instructions. This fixes asm printer crashes when compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run with -O0 to check this in the future. Prior to this change VLDM/VSTM used addressing mode #5, but not really. The offset field was used to hold a count of the number of registers being loaded or stored, and the AM5 opcode field was expanded to specify the IA or DB mode, instead of the standard ADD/SUB specifier. Much of the backend was not aware of these special cases. The crashes occured when rewriting a frameindex caused the AM5 offset field to be changed so that it did not have a valid submode. I don't know exactly what changed to expose this now. Maybe we've never done much with -O0 and NEON. Regardless, there's no longer any reason to keep a count of the VLDM/VSTM registers, so we can use addressing mode #4 and clean things up in a lot of places. llvm-svn: 112322
* Minor simplification. Gets rid of a needless temporary.Bill Wendling2010-08-181-4/+3
| | | | llvm-svn: 111430
* Handle ARM compares as well as converting for ARM adds, subs, and thumb2's adds.Bill Wendling2010-08-111-0/+5
| | | | llvm-svn: 110762
* Turn optimize compares back on with fix. We needed to test that a machine op wasBill Wendling2010-08-101-1/+1
| | | | | | a register before checking if it was defined. llvm-svn: 110733
* Use the "isCompare" machine instruction attribute instead of calling theBill Wendling2010-08-081-3/+3
| | | | | | | | | relatively expensive comparison analyzer on each instruction. Also rename the comparison analyzer method to something more in line with what it actually does. This pass is will eventually be folded into the Machine CSE pass. llvm-svn: 110539
* Add the Optimize Compares pass (disabled by default).Bill Wendling2010-08-061-0/+56
| | | | | | | | | | | | | | | | This pass tries to remove comparison instructions when possible. For instance, if you have this code: sub r1, 1 cmp r1, 0 bz L1 and "sub" either sets the same flag as the "cmp" instruction or could be converted to set the same flag, then we can eliminate the "cmp" instruction all together. This is a important for ARM where the ALU instructions could set the CPSR flag, but need a special suffix ('s') to do so. llvm-svn: 110423
* Many Thumb2 instructions can reference the full ARM register set (i.e.,Jim Grosbach2010-07-301-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | have 4 bits per register in the operand encoding), but have undefined behavior when the operand value is 13 or 15 (SP and PC, respectively). The trivial coalescer in linear scan sometimes will merge a copy from SP into a subsequent instruction which uses the copy, and if that instruction cannot legally reference SP, we get bad code such as: mls r0,r9,r0,sp instead of: mov r2, sp mls r0, r9, r0, r2 This patch adds a new register class for use by Thumb2 that excludes the problematic registers (SP and PC) and is used instead of GPR for those operands which cannot legally reference PC or SP. The trivial coalescer explicitly requires that the register class of the destination for the COPY instruction contain the source register for the COPY to be considered for coalescing. This prevents errant instructions like that above. PR7499 llvm-svn: 109842
* prune #includes a little.Chris Lattner2010-07-201-1/+1
| | | | llvm-svn: 108929
* Remove the isMoveInstr() hook.Jakob Stoklund Olesen2010-07-161-42/+0
| | | | llvm-svn: 108567
* Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission andBill Wendling2010-07-161-1/+1
| | | | | | thus is a much more meaningful name. llvm-svn: 108563
* RISC architectures get their memory operand folding for free.Jakob Stoklund Olesen2010-07-111-217/+0
| | | | | | | | The only folding these load/store architectures can do is converting COPY into a load or store, and the target independent part of foldMemoryOperand already knows how to do that. llvm-svn: 108099
* Replace copyRegToReg with copyPhysReg for ARM.Jakob Stoklund Olesen2010-07-111-77/+36
| | | | llvm-svn: 108078
* Automatically fold COPY instructions into stack load/store.Jakob Stoklund Olesen2010-07-091-1/+1
| | | | llvm-svn: 108012
* For big-endian systems, VLD2/VST2 with 32-bit vector elements will swap theBob Wilson2010-07-081-2/+2
| | | | | | | words within the 64-bit D registers. Use VLD1/VST1 with 64-bit elements instead. llvm-svn: 107890
* Represent NEON load/store alignments in bytes, not bits.Bob Wilson2010-07-061-6/+6
| | | | llvm-svn: 107701
* Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversionRafael Espindola2010-07-061-4/+6
| | | | | | if profitable. llvm-svn: 107673
* Add a VT argument to getMinimalPhysRegClass and replace the copy related usesRafael Espindola2010-06-291-0/+5
| | | | | | | | | of getPhysicalRegisterRegClass with it. If we want to make a copy (or estimate its cost), it is better to use the smallest class as more efficient operations might be possible. llvm-svn: 107140
* Change if-conversion block size limit checks to add some flexibility.Evan Cheng2010-06-251-0/+18
| | | | llvm-svn: 106901
* IT instructions are considered to be scheduling hazards, but are scheduledJim Grosbach2010-06-251-1/+13
| | | | | | | | | | | | with the following instructions. This is done via trickery by considering the instruction preceding the IT to be the hazard. Care must be taken to ensure it's the first non-debug instruction, or the presence of debug info will affect codegen. Part of the continuing work for rdar://7797940, making ARM code-gen unaffected by the presence of debug information. llvm-svn: 106871
* We are missing opportunites to use ldm. Take code like this:Bill Wendling2010-06-231-0/+101
| | | | | | | | | | | | | | void t(int *cp0, int *cp1, int *dp, int fmd) { int c0, c1, d0, d1, d2, d3; c0 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000); c1 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000); /* ... */ } It code gens into something pretty bad. But with this change (analogous to the X86 back-end), it will use ldm and generate few instructions. llvm-svn: 106693
* Allow ARM if-converter to be run after post allocation scheduling.Evan Cheng2010-06-181-0/+28
| | | | | | | | | | | | | | | | - This fixed a number of bugs in if-converter, tail merging, and post-allocation scheduler. If-converter now runs branch folding / tail merging first to maximize if-conversion opportunities. - Also changed the t2IT instruction slightly. It now defines the ITSTATE register which is read by instructions in the IT block. - Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't change the instruction ordering in the IT block (since IT mask has been finalized). It also ensures no other instructions can be scheduled between instructions in the IT block. This is not yet enabled. llvm-svn: 106344
* Rewrite chained if's as switches and replace assertions with llvm_unreachableBob Wilson2010-06-181-35/+55
| | | | | | (as suggested in radar 8104405). llvm-svn: 106318
* Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). ThisStuart Hastings2010-06-171-9/+7
| | | | | | | | | | | | addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. llvm-svn: 106243
* Next round of tail call changes. Register used in a tailDale Johannesen2010-06-151-6/+7
| | | | | | | | call must not be callee-saved; following x86, add a new regclass to represent this. Also fixes a couple of bugs. Still disabled by default; Thumb doesn't work yet. llvm-svn: 106053
* VMOVQQ and VMOVQQQQ are pseudo instructions and not predicable.Bob Wilson2010-06-151-1/+4
| | | | llvm-svn: 105990
* Reapply r105521, this time appending "LLU" to 64 bitBruno Cardoso Lopes2010-06-081-2/+2
| | | | | | immediates to avoid breaking the build. llvm-svn: 105652
* revert r105521, which is breaking the buildbots with stuff like this:Chris Lattner2010-06-051-2/+2
| | | | | | | | | | | | | | In file included from X86InstrInfo.cpp:16: X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type llvm-svn: 105524
* Initial AVX support for some instructions. No patterns matchedBruno Cardoso Lopes2010-06-051-2/+2
| | | | | | yet, only assembly encoding support. llvm-svn: 105521
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