| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [IR] Refactor attribute methods in Function class (NFC) | Evandro Menezes | 2019-04-04 | 1 | -3/+3 |
| * | [ARM] Don't try to create "push {r12, lr}" in Thumb1 at -Oz. | Eli Friedman | 2019-04-01 | 1 | -0/+2 |
| * | [ARM] Don't confuse the scheduler for very large VLDMDIA etc. | Eli Friedman | 2019-03-27 | 1 | -1/+6 |
| * | [ARM] Add missing memory operands to a bunch of instructions. | Eli Friedman | 2019-03-25 | 1 | -2/+4 |
| * | [ARM] Don't form "ands" when it isn't scheduled correctly. | Eli Friedman | 2019-03-22 | 1 | -1/+9 |
| * | [ARM] Add MachineVerifier logic for some Thumb1 instructions. | Eli Friedman | 2019-03-15 | 1 | -0/+25 |
| * | [ARM] Add some more missing T1 opcodes for the peephole optimisier | David Green | 2019-02-25 | 1 | -12/+24 |
| * | [ARM] Add some missing thumb1 opcodes to enable peephole optimisation of CMPs | David Green | 2019-02-22 | 1 | -11/+54 |
| * | Revert 354564: [ARM] Add some missing thumb1 opcodes to enable peephole optim... | David Green | 2019-02-21 | 1 | -54/+12 |
| * | [ARM] Add some missing thumb1 opcodes to enable peephole optimisation of CMPs | David Green | 2019-02-21 | 1 | -12/+54 |
| * | [ARM] Ensure we update the correct flags in the peephole optimiser | David Green | 2019-02-14 | 1 | -2/+5 |
| * | [ARM] Add OptMinSize to ARMSubtarget | Sam Parker | 2019-02-08 | 1 | -1/+1 |
| * | [ARM] Reformat isRedundantFlagInstr for D57833. NFC | David Green | 2019-02-07 | 1 | -8/+4 |
| * | Update the file headers across all of the LLVM projects in the monorepo | Chandler Carruth | 2019-01-19 | 1 | -4/+3 |
| * | [ARM] Add missing pseudo-instruction for Thumb1 RSBS. | Eli Friedman | 2018-10-31 | 1 | -0/+1 |
| * | [ARM] Make InstrEmitter mark CPSR defs dead for Thumb1. | Eli Friedman | 2018-10-26 | 1 | -0/+2 |
| * | [ARM] Account for implicit IT when calculating inline asm size | Peter Smith | 2018-10-08 | 1 | -2/+6 |
| * | X86, AArch64, ARM: Do not attach debug location to spill/reload instructions | Matthias Braun | 2018-10-05 | 1 | -15/+15 |
| * | Revert "X86, AArch64, ARM: Do not attach debug location to spill/reload instr... | Matt Morehouse | 2018-10-02 | 1 | -15/+15 |
| * | X86, AArch64, ARM: Do not attach debug location to spill/reload instructions | Matthias Braun | 2018-10-01 | 1 | -15/+15 |
| * | llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...) | Fangrui Song | 2018-09-27 | 1 | -3/+2 |
| * | Remove FrameAccess struct from hasLoadFromStackSlot | Sander de Smalen | 2018-09-05 | 1 | -4/+8 |
| * | Extend hasStoreToStackSlot with list of FI accesses. | Sander de Smalen | 2018-09-03 | 1 | -4/+12 |
| * | [MinGW] [ARM] Add stubs for potential automatic dllimported variables | Martin Storsjo | 2018-08-31 | 1 | -0/+1 |
| * | Make TargetInstrInfo::isCopyInstr return true for regular COPY-instructions | Alexander Ivchenko | 2018-08-30 | 1 | -3/+3 |
| * | [ARM] Move machine operand target flags to ARMBaseInstrInfo | Martin Storsjo | 2018-08-22 | 1 | -0/+28 |
| * | [MI] Change the array of `MachineMemOperand` pointers to be | Chandler Carruth | 2018-08-16 | 1 | -8/+7 |
| * | [NEON] Support vldNq intrinsics in AArch32 (LLVM part) | Ivan A. Kosarev | 2018-06-27 | 1 | -0/+18 |
| * | Change TII isCopyInstr way of returning arguments(NFC) | Petar Jovanovic | 2018-06-06 | 1 | -4/+5 |
| * | [NEON] Support VLD1xN intrinsics in AArch32 mode (LLVM part) | Ivan A. Kosarev | 2018-06-02 | 1 | -0/+28 |
| * | Revert r333819 "[NEON] Support VLD1xN intrinsics in AArch32 mode (Clang part)" | Ivan A. Kosarev | 2018-06-02 | 1 | -28/+0 |
| * | [NEON] Support VLD1xN intrinsics in AArch32 mode (Clang part) | Ivan A. Kosarev | 2018-06-02 | 1 | -0/+28 |
| * | [X86][MIPS][ARM] New machine instruction property 'isMoveReg' | Petar Jovanovic | 2018-05-23 | 1 | -0/+18 |
| * | Rename DEBUG macro to LLVM_DEBUG. | Nicola Zaghen | 2018-05-14 | 1 | -2/+2 |
| * | [DebugInfo] Examine all uses of isDebugValue() for debug instructions. | Shiva Chen | 2018-05-09 | 1 | -4/+4 |
| * | Remove \brief commands from doxygen comments. | Adrian Prantl | 2018-05-01 | 1 | -1/+1 |
| * | [ARM] Change std::sort to llvm::sort in response to r327219 | Mandeep Singh Grang | 2018-04-05 | 1 | -6/+6 |
| * | [ARM] Fix codegen for VLD3/VLD4/VST3/VST4 with WB | Florian Hahn | 2018-03-02 | 1 | -0/+2 |
| * | [MachineOperand][Target] MachineOperand::isRenamable semantics changes | Geoff Berry | 2018-02-23 | 1 | -4/+0 |
| * | [ARM] f16 stack spill/reloads | Sjoerd Meijer | 2018-02-14 | 1 | -1/+21 |
| * | [ARM] Armv8.2-A FP16 code generation (part 1/3) | Sjoerd Meijer | 2018-01-26 | 1 | -0/+8 |
| * | [ARM] Cleanup part of ARMBaseInstrInfo::optimizeCompareInstr (NFCI). | Joel Galenson | 2018-01-22 | 1 | -12/+8 |
| * | [ARM] Fix perf regression in compare optimization. | Joel Galenson | 2018-01-19 | 1 | -3/+2 |
| * | [ARM] Optimize {s,u}{add,sub}.with.overflow. | Joel Galenson | 2018-01-17 | 1 | -23/+74 |
| * | PeepholeOptimizer: Fix for vregs without defs | Matthias Braun | 2018-01-11 | 1 | -4/+10 |
| * | [CodeGen] Don't print "pred:" and "opt:" in -debug output | Francis Visoiu Mistrih | 2018-01-09 | 1 | -3/+3 |
| * | [ARM] Fix PR35379 - incorrect unwind information when compiling with -Oz | Momchil Velikov | 2018-01-08 | 1 | -3/+3 |
| * | MachineFunction: Return reference from getFunction(); NFC | Matthias Braun | 2017-12-15 | 1 | -6/+6 |
| * | [CodeGen] Print global addresses as @foo in both MIR and debug output | Francis Visoiu Mistrih | 2017-12-14 | 1 | -1/+1 |
| * | [MachineOperand][MIR] Add isRenamable to MachineOperand. | Geoff Berry | 2017-12-12 | 1 | -4/+13 |
