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path: root/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
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* Clean up ARM subtarget code by using Triple ADT.Evan Cheng2011-01-111-3/+4
| | | | llvm-svn: 123276
* Model operand restrictions of mul-like instructions on ARMv5 viaAnton Korobeynikov2011-01-011-0/+34
| | | | | | | | | earlyclobber stuff. This should fix PRs 2313 and 8157. Unfortunately, no testcase, since it'd be dependent on register assignments. llvm-svn: 122663
* r120333 changed the opcode for the Thumb1 stuff from ARM::tMOVr toBill Wendling2010-12-181-1/+1
| | | | | | | | | | | ARM::tMOVgpr2gpr. But this check didn't change. As a result, we were getting misaligned references to the jump table from an ADR instruction. There is a test case, but unfortunately it's sensitive to random code changes. <rdar://problem/8782223> llvm-svn: 122131
* Avoid report_fatal_error in ARM's PrintAsmOperand method.Bob Wilson2010-12-171-1/+1
| | | | | | | The standard error handling in AsmPrinter::EmitInlineAsm handles this much better, so just use it. llvm-svn: 122100
* Pseudo-ize the Thumb1 tBfar pattern. rdar://8777974Jim Grosbach2010-12-161-0/+8
| | | | llvm-svn: 121990
* Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755Jim Grosbach2010-12-141-6/+10
| | | | llvm-svn: 121798
* Refactor a bit for legibility.Jim Grosbach2010-12-141-28/+27
| | | | llvm-svn: 121790
* Make sure to propagate the predicate operands for LEApcrel to ADR.Jim Grosbach2010-12-141-4/+4
| | | | llvm-svn: 121788
* The tLDR et al instructions were emitting either a reg/reg or reg/immBill Wendling2010-12-141-9/+5
| | | | | | | | | | | | | | | | instruction based on the t_addrmode_s# mode and what it returned. There is some obvious badness to this. In particular, it's hard to do MC-encoding when the instruction may change out from underneath you after the t_addrmode_s# variable is finally resolved. The solution is to revert a long-ago change that merged the reg/reg and reg/imm versions. There is the addition of several new addressing modes. They no longer have extraneous operands associated with them. I.e., if it's reg/reg we don't have to have a dummy zero immediate tacked on to the SDNode. There are some obvious cleanups here, which will happen shortly. llvm-svn: 121747
* Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering ↵Owen Anderson2010-12-141-2/+10
| | | | | | | | much later, which makes the entire process cleaner. llvm-svn: 121735
* Add a textual message to the assert.Jim Grosbach2010-12-091-1/+2
| | | | llvm-svn: 121349
* Add a sanity check assert() for t2ADD/SUBrSPi instructions that they really areJim Grosbach2010-12-091-0/+7
| | | | | | referencing the stack pointer as they say they are. llvm-svn: 121347
* Add support for binary encoding of ARM 'adr' instructions referencing constantJim Grosbach2010-12-021-1/+17
| | | | | | pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291. llvm-svn: 120635
* Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADRJim Grosbach2010-12-011-0/+15
| | | | | | | instruction at MC lowering. Add binary encoding information for the ADR, including fixup data for the label operand. llvm-svn: 120594
* Move the ARMAsmPrinter class defintiion into a header file.Jim Grosbach2010-12-011-94/+14
| | | | llvm-svn: 120551
* Pseudo-ize ARM MOVPCRXJim Grosbach2010-11-301-0/+13
| | | | llvm-svn: 120442
* Pseudo-ize BX_CALL and friends. Remove dead instruction format classes.Jim Grosbach2010-11-301-0/+53
| | | | | | rdar://8685712 llvm-svn: 120438
* s/ARM::BRIND/ARM::BX/g to coincide with r120366.Bill Wendling2010-11-301-1/+1
| | | | llvm-svn: 120371
* Pseudo-ize Thumb2 jump tables with explicit MC lowering to the rawJim Grosbach2010-11-291-11/+41
| | | | | | instructions. This simplifies instruction printing and disassembly. llvm-svn: 120333
* Rename t2 TBB and TBH instructions to reference that they encode the jump tableJim Grosbach2010-11-291-5/+5
| | | | | | data. Next up, pseudo-izing them. llvm-svn: 120320
* ARM Pseudo-ize tBR_JTr.Jim Grosbach2010-11-291-13/+7
| | | | llvm-svn: 120310
* Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos.Jim Grosbach2010-11-291-12/+54
| | | | llvm-svn: 120303
* Make the ARM BR_JTadd instruction an explicit pseudo and lower it properlyJim Grosbach2010-11-171-2/+20
| | | | | | in the MC lowering process. llvm-svn: 119559
* Add FIXMEs.Jim Grosbach2010-11-151-0/+4
| | | | llvm-svn: 119167
* add fields to the .td files unconditionally, simplifying tblgen a bit.Chris Lattner2010-11-151-1/+1
| | | | | | Switch the ARM backend to use 'let' instead of 'set' with this change. llvm-svn: 119120
* rename LowerToMCInst -> LowerARMMachineInstrToMCInst.Chris Lattner2010-11-141-3/+3
| | | | llvm-svn: 119071
* even more simplifications. ARM MCInstLowering is now justChris Lattner2010-11-141-5/+3
| | | | | | | a single function instead of a class. It doesn't need the complexity that X86 does. llvm-svn: 119070
* simplify and tidy upChris Lattner2010-11-141-2/+1
| | | | llvm-svn: 119066
* Simplify and clean up MC symbol lookup for ARM constant pool values. This fixesJim Grosbach2010-11-101-10/+10
| | | | | | | | double quoting of ObjC symbol names in constant pool entries. rdar://8652107 llvm-svn: 118688
* Update ARMConstantPoolValue to not use a modifier string. Use an explicitJim Grosbach2010-11-101-47/+38
| | | | | | | VariantKind marker to indicate the additional information necessary. Update MC to handle the new Kinds. rdar://8647623 llvm-svn: 118671
* Change the ARMConstantPoolValue modifier string to an enumeration. This willJim Grosbach2010-11-091-1/+1
| | | | | | help in MC'izing the references that use them. llvm-svn: 118633
* Handle ARM constant pool values that need an explicit reference to the '.'Jim Grosbach2010-11-091-1/+9
| | | | | | pseudo-label. (TLS stuff). llvm-svn: 118609
* Further MCize ARM constant pool values. This allows basic PIC references forJim Grosbach2010-11-091-67/+83
| | | | | | object file emission. llvm-svn: 118601
* Revert 118422 in search of bot verdancy.Dale Johannesen2010-11-081-44/+10
| | | | llvm-svn: 118429
* Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified.Jason W Kim2010-11-081-10/+44
| | | | llvm-svn: 118422
* MC'ize the '.code 16' and '.thumb_func' ARM directives.Jim Grosbach2010-11-051-11/+2
| | | | llvm-svn: 118301
* MC'ize simple ARMConstantValue entry emission (with a FIXME).Jim Grosbach2010-11-051-28/+37
| | | | llvm-svn: 118295
* Add FIXME.Jim Grosbach2010-11-051-0/+1
| | | | llvm-svn: 118280
* Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it inJim Grosbach2010-10-291-38/+0
| | | | | | the ARMExpandPseudos pass rather than during the asm lowering. llvm-svn: 117714
* ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need toJim Grosbach2010-10-291-55/+0
| | | | | | handle it in the asm lowering. llvm-svn: 117707
* Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, likeJim Grosbach2010-10-271-4/+3
| | | | | | | | the LDR instructions have. This makes the literal/register forms of the instructions explicit and allows us to assign scheduling itineraries appropriately. rdar://8477752 llvm-svn: 117505
* Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing onJim Grosbach2010-10-271-1/+1
| | | | | | rdar://8477752. llvm-svn: 117419
* First part of refactoring ARM addrmode2 (load/store) instructions to be moreJim Grosbach2010-10-261-7/+4
| | | | | | | | explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
* Produce the headers directly in the Finish method. This allows us to useRafael Espindola2010-10-251-21/+15
| | | | | | the existing streamer methods that are endian safe. llvm-svn: 117323
* Add a virtual destructor.Rafael Espindola2010-10-251-0/+1
| | | | llvm-svn: 117280
* Add support for emitting ARM file attributes.Rafael Espindola2010-10-251-37/+123
| | | | llvm-svn: 117275
* Second set of ARM/MC/ELF changes.Jason W Kim2010-10-111-5/+43
| | | | | | | | | Added ARM specific ELF section types. Added AttributesSection to ARMElfTargetObject First step in unifying .cpu assembly tag with ELF/.o llc now asserts on actual ELF emission on -filetype=obj :-) llvm-svn: 116257
* remove trailing whitespaceJim Grosbach2010-10-061-5/+5
| | | | llvm-svn: 115860
* First in a sequence of ARM/MC/*ELF* specific work.Jason W Kim2010-10-061-38/+59
| | | | | | | | | Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute() Added ARMAsmPrinter::emitAttributes() (plural s). TODO: .cpu attribute needs to be refactored llvm-svn: 115859
* Kill of the vestiges of the 'call' Modifier (no longer needed for PLT).Jim Grosbach2010-10-061-9/+2
| | | | llvm-svn: 115845
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