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| author | Jim Grosbach <grosbach@apple.com> | 2010-10-26 22:37:02 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-10-26 22:37:02 +0000 |
| commit | 1e4d9a17c21fd5c9908024df450bae31d160ebd3 (patch) | |
| tree | 4afd47f1dcc562f1c72fd6af47a687555baebb62 /llvm/lib/Target/ARM/ARMAsmPrinter.cpp | |
| parent | e4f3317cdaacdf5dadbcf0afb4940af311588e19 (diff) | |
| download | bcm5719-llvm-1e4d9a17c21fd5c9908024df450bae31d160ebd3.tar.gz bcm5719-llvm-1e4d9a17c21fd5c9908024df450bae31d160ebd3.zip | |
First part of refactoring ARM addrmode2 (load/store) instructions to be more
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
llvm-svn: 117409
Diffstat (limited to 'llvm/lib/Target/ARM/ARMAsmPrinter.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp index 01ad2f5ad8a..e334307c67c 100644 --- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp @@ -873,7 +873,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { case ARM::PICSTR: Opcode = ARM::STR; break; case ARM::PICSTRB: Opcode = ARM::STRB; break; case ARM::PICSTRH: Opcode = ARM::STRH; break; - case ARM::PICLDR: Opcode = ARM::LDR; break; + case ARM::PICLDR: Opcode = ARM::LDRrs; break; case ARM::PICLDRB: Opcode = ARM::LDRB; break; case ARM::PICLDRH: Opcode = ARM::LDRH; break; case ARM::PICLDRSB: Opcode = ARM::LDRSB; break; @@ -1220,10 +1220,9 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { unsigned ScratchReg = MI->getOperand(1).getReg(); { MCInst TmpInst; - TmpInst.setOpcode(ARM::LDR); + TmpInst.setOpcode(ARM::LDRi12); TmpInst.addOperand(MCOperand::CreateReg(ARM::SP)); TmpInst.addOperand(MCOperand::CreateReg(SrcReg)); - TmpInst.addOperand(MCOperand::CreateReg(0)); TmpInst.addOperand(MCOperand::CreateImm(8)); // Predicate. TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); @@ -1232,10 +1231,9 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { } { MCInst TmpInst; - TmpInst.setOpcode(ARM::LDR); + TmpInst.setOpcode(ARM::LDRi12); TmpInst.addOperand(MCOperand::CreateReg(ScratchReg)); TmpInst.addOperand(MCOperand::CreateReg(SrcReg)); - TmpInst.addOperand(MCOperand::CreateReg(0)); TmpInst.addOperand(MCOperand::CreateImm(4)); // Predicate. TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); @@ -1244,10 +1242,9 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { } { MCInst TmpInst; - TmpInst.setOpcode(ARM::LDR); + TmpInst.setOpcode(ARM::LDRi12); TmpInst.addOperand(MCOperand::CreateReg(ARM::R7)); TmpInst.addOperand(MCOperand::CreateReg(SrcReg)); - TmpInst.addOperand(MCOperand::CreateReg(0)); TmpInst.addOperand(MCOperand::CreateImm(0)); // Predicate. TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); |
