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path: root/llvm/lib/Target/AMDGPU/VOPInstructions.td
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* [AMDGPU] copy OtherPredicates from pseudo to VOP3_RealStanislav Mekhanoshin2019-09-261-0/+1
* AMDGPU: Move MnemonicAlias out of instruction def hierarchyMatt Arsenault2019-09-091-7/+4
* [AMDGPU] gfx908 mAI instructions, MC partStanislav Mekhanoshin2019-07-091-0/+31
* [AMDGPU] gfx1010 dpp16 and dpp8Stanislav Mekhanoshin2019-06-121-5/+42
* [AMDGPU] gfx1010 VOP1 instructionsStanislav Mekhanoshin2019-04-251-11/+93
* AMDGPU: Remove GCN features and predicatesMatt Arsenault2019-02-081-1/+0
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [AMDGPU] Combine DPP mov with use instructions (VOP1/2/3)Valery Pykhtin2018-11-301-3/+43
* [AMDGPU] Divergence driven instruction selection. Shift operations.Alexander Timofeev2018-10-011-0/+5
* AMDGPU: Split HasExt into HasExtDPP/SDWA/SDWA9Konstantin Zhuravlyov2018-09-271-11/+11
* [AMDGPU] Divergence driven instruction selection. Part 1.Alexander Timofeev2018-09-211-0/+44
* AMDGPU: Introduce common SOP_Pseudo and VOP_Pseudo TableGen base classesNicolai Haehnle2018-03-261-20/+27
* [AMDGPU][MC] Corrected default values for unused SDWA operandsDmitry Preobrazhensky2018-03-161-8/+8
* [MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry2018-02-231-2/+0
* [AMDGPU] isRenamable fixes to support copy forwardingGeoff Berry2018-01-301-0/+2
* [AMDGPU] Copy impdefs from pseudo to real instructionsStanislav Mekhanoshin2018-01-151-0/+1
* [AMDGPU][MC][GFX9][disassembler] Corrected decoding of op_sel_hi for v_mad_mix*Dmitry Preobrazhensky2017-11-171-5/+5
* AMDGPU: Fold clamp modifier for packed instructionsMatt Arsenault2017-08-311-0/+4
* AMDGPU: Correct operand types for v_mad_mix*Matt Arsenault2017-08-301-3/+4
* [AMDGPU][MC][GFX9] Added integer clamping support for VOP3 opcodesDmitry Preobrazhensky2017-08-161-1/+1
* [AMDGPU] Add pseudo "old" source to all DPP instructionsConnor Abbott2017-08-071-0/+2
* [AMDGPU][MC] Corrected VOP3 version of v_interp_* instructions for VIDmitry Preobrazhensky2017-08-071-0/+19
* [AMDGPU][MC][GFX9] Added support of VOP3 'op_sel' modifierDmitry Preobrazhensky2017-07-211-6/+21
* [AMDGPU] resubmit r308179: CodeGen: check dst operand type to determine if om...Sam Kolton2017-07-181-0/+2
* Revert r308179 which causes tablegen to spam stderr on every build.Chandler Carruth2017-07-181-2/+0
* [AMDGPU] CodeGen: check dst operand type to determine if omod is supported fo...Sam Kolton2017-07-171-0/+2
* [AMDGPU] Assembler: refactor convert methods (VOP3 and MIMG)Sam Kolton2017-07-071-12/+6
* [AMDGPU] SDWA: add support for GFX9 in peephole passSam Kolton2017-06-221-4/+0
* [AMDGPU][MC][GFX9] Corrected VOP3P relevant code to fix disassembler failuresDmitry Preobrazhensky2017-06-211-6/+6
* [AMDGPU] SDWA: merge VI and GFX9 pseudo instructionsSam Kolton2017-06-211-52/+28
* [AMDGPU] SDWA: Add assembler support for GFX9Sam Kolton2017-05-231-1/+113
* [AMDGPU][MC] Fix for Bug 28207 + LIT testsDmitry Preobrazhensky2017-03-271-2/+6
* [ADMGPU] SDWA peephole optimization pass.Sam Kolton2017-03-211-1/+1
* [AMDGPU][MC] Fix for Bug 30829 + LIT testsDmitry Preobrazhensky2017-03-031-0/+2
* AMDGPU: Add VOP3P instruction formatMatt Arsenault2017-02-271-4/+53
* AMDGPU: Fold FP clamp as modifier bitMatt Arsenault2017-02-221-0/+1
* AMDGPU: Fix trailing whitespaceMatt Arsenault2017-02-101-3/+3
* [AMDGPU] Add subtarget features for SDWA/DPPSam Kolton2017-01-201-4/+4
* [AMDGPU] Add pseudo SDWA instructionsSam Kolton2016-12-221-14/+67
* [AMDGPU] Disassembler: fix for disaasembling v_mac_f32/16_dpp/sdwaSam Kolton2016-12-221-0/+3
* Fix spelling mistakes in AMDGPU target comments. NFC.Simon Pilgrim2016-11-181-2/+2
* AMDGPU: Move redundant setting of inst propertiesMatt Arsenault2016-11-181-3/+1
* [AMDGPU] Refactor VOP1 and VOP2 instruction TD definitionsValery Pykhtin2016-09-231-27/+149
* [AMDGPU] Refactor VOP3 instruction TD definitionsValery Pykhtin2016-09-201-0/+44
* [AMDGPU] Refactor VOPC instruction TD definitionsValery Pykhtin2016-09-191-0/+130
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