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path: root/llvm/lib/Target/AMDGPU/VOP3Instructions.td
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* AMDGPU/GlobalISel: Select G_ASHRMatt Arsenault2019-07-161-1/+1
* AMDGPU/GlobalISel: Select G_LSHRMatt Arsenault2019-07-161-1/+1
* AMDGPU/GlobalISel: Select G_SHLMatt Arsenault2019-07-161-1/+1
* [AMDGPU] gfx908 mAI instructions, MC partStanislav Mekhanoshin2019-07-091-7/+17
* AMDGPU/GlobalISel: Select mulMatt Arsenault2019-07-021-1/+1
* [AMDGPU] gfx1010 core wave32 changesStanislav Mekhanoshin2019-06-201-2/+2
* [AMDGPU] gfx1010 premlane instructionsStanislav Mekhanoshin2019-06-121-0/+28
* [AMDGPU] Pattern for v_xor3_b32Stanislav Mekhanoshin2019-05-101-1/+4
* [AMDGPU] gfx1010 VOP3 and VOP3P implementationStanislav Mekhanoshin2019-04-261-102/+236
* [AMDGPU] gfx1010 VOP1 instructionsStanislav Mekhanoshin2019-04-251-4/+4
* [AMDGPU] Sort out and rename multiple CI/VI predicatesStanislav Mekhanoshin2019-04-061-15/+15
* [AMDGPU] predicate and feature refactoringStanislav Mekhanoshin2019-04-051-22/+29
* [AMDGPU] Asm/disasm v_cndmask_b32_e64 with abs/neg source modifiersTim Renouf2019-03-181-0/+1
* Revert "AMDGPU/NFC: Cleanup subtarget predicates"Konstantin Zhuravlyov2019-02-221-27/+27
* AMDGPU/NFC: Cleanup subtarget predicatesKonstantin Zhuravlyov2019-02-211-27/+27
* [AMDGPU] Add intrinsics for 16 bit interpolationTim Corringham2019-01-281-3/+24
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [AMDGPU] Add new Mode Register passTim Corringham2018-12-101-8/+28
* AMDGPU: Generate VALU ThreeOp Integer instructionsNicolai Haehnle2018-12-061-0/+47
* AMDGPU: Fix V_FMA_F16 selection on GFX9Konstantin Zhuravlyov2018-11-191-2/+8
* DAG: Change behavior of fminnum/fmaxnum nodesMatt Arsenault2018-10-221-2/+2
* [AMDGPU] Divergence driven instruction selection. Shift operations.Alexander Timofeev2018-10-011-20/+37
* AMDGPU: Fix getInstSizeInBytesNicolai Haehnle2018-08-291-8/+11
* AMDGPU: Remove broken i16 ternary patternsJan Vesely2018-08-071-11/+0
* [AMDGPU] DAG combine to produce V_PERM_B32Stanislav Mekhanoshin2018-06-121-1/+1
* AMDGPU: Fix v_dot{4, 8}* instruction encodingKonstantin Zhuravlyov2018-05-151-4/+9
* [AMDGPU] Fixed some instructions latenciesStanislav Mekhanoshin2018-03-301-5/+6
* AMDGPU: Introduce common SOP_Pseudo and VOP_Pseudo TableGen base classesNicolai Haehnle2018-03-261-3/+3
* [AMDGPU] Fixed V_DIV_FIXUP_F16 selection on GFX9Stanislav Mekhanoshin2018-03-091-13/+12
* [AMDGPU] isRenamable fixes to support copy forwardingGeoff Berry2018-01-301-2/+0
* [AMDGPU][MC][GFX9] Added v_interp_p2_f16 and v_interp_p2_legacy_f16Dmitry Preobrazhensky2017-11-241-2/+18
* [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/su...Dmitry Preobrazhensky2017-11-201-2/+16
* AMDGPU: Set correct sched model on v_mad_u64_u32Matt Arsenault2017-11-081-0/+2
* AMDGPU: Remove global isGCN predicatesMatt Arsenault2017-10-031-4/+4
* [AMDGPU][MC][GFX9] Added op_sel support for v_mad_*16, v_fma_f16, v_div_fixup...Dmitry Preobrazhensky2017-08-161-66/+85
* [AMDGPU][MC][GFX9] Added integer clamping support for VOP3 opcodesDmitry Preobrazhensky2017-08-161-20/+84
* [AMDGPU][MC][GFX9] Added 16-bit renamed and "_legacy" VALU opcodesDmitry Preobrazhensky2017-08-091-13/+57
* [AMDGPU][MC] Corrected VOP3 version of v_interp_* instructions for VIDmitry Preobrazhensky2017-08-071-6/+83
* [AMDGPU][MC][GFX9] Added support of VOP3 'op_sel' modifierDmitry Preobrazhensky2017-07-211-20/+98
* [AMDGPU] resubmit r308179: CodeGen: check dst operand type to determine if om...Sam Kolton2017-07-181-3/+8
* Revert r308179 which causes tablegen to spam stderr on every build.Chandler Carruth2017-07-181-7/+3
* [AMDGPU] CodeGen: check dst operand type to determine if omod is supported fo...Sam Kolton2017-07-171-3/+7
* [AMDGPU] Add intrinsics for alignbit and alignbyte instructionsStanislav Mekhanoshin2017-06-091-2/+2
* [AMDGPU] Force qsads instrs to use different dest register than source registersMark Searles2017-06-081-0/+5
* [AMDGPU] V_DIV_FIXUP_F16 is not a commutable operationStanislav Mekhanoshin2017-06-031-1/+2
* [AMDGPU] SDWA: Add assembler support for GFX9Sam Kolton2017-05-231-4/+5
* AMDGPU: Fix min3/max3 combines for f16/i16Matt Arsenault2017-05-171-1/+19
* [AMDGPU][MC] Removed V_MQSAD_U16_U8Dmitry Preobrazhensky2017-05-151-3/+0
* [AMDGPU][MC] Added support for several VI-specific opcodes (s_wakeup, etc)Dmitry Preobrazhensky2017-04-121-0/+4
* [AMDGPU][MC] Corrected encoding of V_MQSAD_U32_U8 for CIDmitry Preobrazhensky2017-04-121-1/+1
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