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* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [AMDGPU] Refactor VOP1 and VOP2 instruction TD definitionsValery Pykhtin2016-09-231-157/+0
| | | | | | Differential revision: https://reviews.llvm.org/D24738 llvm-svn: 282234
* [AMDGPU] Refactor VOPC instruction TD definitionsValery Pykhtin2016-09-191-21/+0
| | | | | | Differential Revision: https://reviews.llvm.org/D24546 llvm-svn: 281903
* [AMDGPU] Refactor MUBUF/MTBUF instructionsValery Pykhtin2016-09-101-58/+0
| | | | | | Differential revision: https://reviews.llvm.org/D24295 llvm-svn: 281137
* [AMDGPU] Assembler: match e32 VOP instructions before e64.Sam Kolton2016-09-091-0/+2
| | | | | | | | | | | | | | | | | | | Summary: Split assembler match table in 4 tables with assembler variants: Default - all instructions except VOP3, SDWA and DPP - VOP3 - SDWA - DPP First match Default table then VOP3, SDWA and DPP. Reviewers: tstellarAMD, artem.tamazov, vpykhtin Subscribers: arsenm, wdng, nhaehnle, AMDGPU Differential Revision: https://reviews.llvm.org/D24252 llvm-svn: 281023
* [AMDGPU] Scalar Memory instructions TD refactoringValery Pykhtin2016-09-011-23/+0
| | | | | | Differential revision: https://reviews.llvm.org/D23996 llvm-svn: 280349
* [AMDGPU] refactor DS instruction definitions. NFC.Valery Pykhtin2016-08-011-20/+0
| | | | | | Differential revision: https://reviews.llvm.org/D22522 llvm-svn: 277344
* [AMDGPU] Assembler: support SDWA for VOPC instructionsSam Kolton2016-07-011-0/+4
| | | | | | | | | | | | Summary: dst_sel and dst_unused disabled for VOPC as they have no effect on result Reviewers: artem.tamazov, tstellarAMD, vpykhtin Subscribers: arsenm, kzhuravl Differential Revision: http://reviews.llvm.org/D21376 llvm-svn: 274340
* [AMDGPU] Assembler: More tests for SDWA instructions. Fix for SDWA float ↵Sam Kolton2016-06-031-4/+8
| | | | | | | | | | | | | | modifiers. Summary: Depends on D20625 Reviewers: tstellarAMD, vpykhtin, artem.tamazov Subscribers: arsenm, kzhuravl Differential Revision: http://reviews.llvm.org/D20674 llvm-svn: 271662
* [TableGen] AsmMatcher: support for default values for optional operandsSam Kolton2016-05-061-1/+1
| | | | | | | | | | | | | | Summary: This change allows to specify "DefaultMethod" for optional operand (IsOptional = 1) in AsmOperandClass that return default value for operand. This is used in convertToMCInst to set default values in MCInst. Previously if you wanted to set default value for operand you had to create custom converter method. With this change it is possible to use standard converters even when optional operands presented. Reviewers: tstellarAMD, ab, craig.topper Subscribers: jyknight, dsanders, arsenm, nhaustov, llvm-commits Differential Revision: http://reviews.llvm.org/D18242 llvm-svn: 268726
* [AMDGPU] Assembler: basic support for SDWA instructionsSam Kolton2016-04-261-0/+55
| | | | | | | | | | | | | | | Support for SDWA instructions for VOP1 and VOP2 encoding. Not done yet: - converters for support optional operands and modifiers - VOPC - sext() modifier - intrinsics - VOP2b (see vop_dpp.s) - V_MAC_F32 (see vop_dpp.s) Differential Revision: http://reviews.llvm.org/D19360 llvm-svn: 267553
* [AMDGPU] Fix SMEM instructions encoding/operand namingsValery Pykhtin2016-03-101-3/+11
| | | | | | Differential Revision: http://reviews.llvm.org/D17651 llvm-svn: 263108
* [AMDGPU] Assembler: Support DPP instructions.Sam Kolton2016-03-091-2/+5
| | | | | | | | | | | | | | | | | | | | Supprot DPP syntax as used in SP3 (except several operands syntax). Added dpp-specific operands in td-files. Added DPP flag to TSFlags to determine if instruction is dpp in InstPrinter. Support for VOP2 DPP instructions in td-files. Some tests for DPP instructions. ToDo: - VOP2bInst: - vcc is considered as operand - AsmMatcher doesn't apply mnemonic aliases when parsing operands - v_mac_f32 - v_nop - disable instructions with 64-bit operands - change dpp_ctrl assembler representation to conform sp3 Review: http://reviews.llvm.org/D17804 llvm-svn: 263008
* [AMDGPU] Rename $dst operand to $vdst for VOP instructions.Tom Stellard2016-02-161-7/+19
| | | | | | | | | | | | | | Summary: This change renames output operand for VOP instructions from dst to vdst. This is needed to enable decoding named operands for disassembler. Reviewers: vpykhtin, tstellarAMD, arsenm Subscribers: arsenm, llvm-commits, nhaustov Projects: #llvm-amdgpu-spb Differential Revision: http://reviews.llvm.org/D16920 llvm-svn: 260986
* AMDGPU/SI: Add instruction defs for VOP1 DPP instructionsTom Stellard2016-02-131-0/+45
| | | | | | | | | | Reviewers: nhaustov, cfang, arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D17159 llvm-svn: 260774
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+166
llvm-svn: 239657
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