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path: root/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
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* AMDGPU: Remove dx10-clamp from subtarget featuresMatt Arsenault2019-03-291-0/+13
* [AMDGPU] Added v5i32 and v5f32 register classesTim Renouf2019-03-221-0/+4
* [AMDGPU] Support for v3i32/v3f32Tim Renouf2019-03-211-0/+2
* [AMDGPU][MC] Enable lds_direct operand for v_readfirstlane_b32, v_readlane_b3...Dmitry Preobrazhensky2019-03-041-0/+2
* AMDGPU: Remove GCN features and predicatesMatt Arsenault2019-02-081-1/+2
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [AMDGPU] Extend the SI Load/Store optimizer to combine more things.Neil Henning2018-12-121-0/+43
* AMDGPU: Divergence-driven selection of scalar buffer load intrinsicsNicolai Haehnle2018-11-301-2/+5
* AMDGPU/InsertWaitcnts: Untangle some semi-global stateNicolai Haehnle2018-11-291-0/+12
* [AMDGPU] Add FixupVectorISel pass, currently Supports SREGs in GLOBAL LD/STRon Lieberman2018-11-161-0/+1
* AMDHSA: More code object v3 fixes:Konstantin Zhuravlyov2018-11-151-1/+2
* Revert "AMDGPU: Divergence-driven selection of scalar buffer load intrinsics"Nicolai Haehnle2018-11-071-5/+2
* AMDGPU: Add sram-ecc featureKonstantin Zhuravlyov2018-11-051-0/+6
* AMDGPU: Divergence-driven selection of scalar buffer load intrinsicsNicolai Haehnle2018-10-171-2/+5
* AMDGPU: Re-apply r341982 after fixing the layering issueKonstantin Zhuravlyov2018-09-121-138/+88
* Revert "AMDGPU: Move isa version and EF_AMDGPU_MACH_* determination into Targ...Ilya Biryukov2018-09-121-88/+138
* AMDGPU: Move isa version and EF_AMDGPU_MACH_* determinationKonstantin Zhuravlyov2018-09-111-138/+88
* AMDGPU: Remove remnants of old address space mappingMatt Arsenault2018-08-311-23/+0
* [AMDGPU] New buffer intrinsicsTim Renouf2018-08-211-0/+43
* [AMDGPU] Optimize _L image intrinsic to _LZ when lod is zeroRyan Taylor2018-08-011-0/+1
* AMDGPU: Separate R600 and GCN TableGen filesTom Stellard2018-06-281-7/+7
* [AMDGPU] Update assembler for HSA Code Object v3Scott Linder2018-06-211-0/+58
* AMDGPU: Select MIMG instructions manually in SITargetLoweringNicolai Haehnle2018-06-211-0/+9
* AMDGPU: Refactor MIMG instruction TableGen using generic tablesNicolai Haehnle2018-06-211-71/+15
* AMDGPU: Use generic tables instead of SearchableTableNicolai Haehnle2018-06-211-3/+3
* AMDHSA: Code object v3 updatesKonstantin Zhuravlyov2018-06-121-2/+2
* AMDGPU : Recalculate SGPRs when trap handler is supportedKonstantin Zhuravlyov2018-05-161-5/+9
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-011-2/+2
* AMDGPU: Add Vega12 and Vega20Matt Arsenault2018-04-301-0/+4
* [AMDGPU] Enabled v2.16 literals for VOP3PStanislav Mekhanoshin2018-04-171-8/+0
* AMDGPU: Remove max_scratch_backing_memory_byte_size from kernel headerKonstantin Zhuravlyov2018-04-091-1/+1
* AMDGPU: Make isIntrinsicSourceOfDivergence table-drivenNicolai Haehnle2018-04-011-47/+13
* [AMDGPU] Add default ISA version targetsStanislav Mekhanoshin2018-03-061-0/+6
* Pass Divergence Analysis data to Selection DAG to drive divergenceAlexander Timofeev2018-03-051-0/+51
* AMDGPU: Bring processors and features in sync with the specKonstantin Zhuravlyov2018-02-161-2/+0
* [AMDGPU] Change constant addr space to 4Yaxun Liu2018-02-131-1/+1
* Reapply "AMDGPU: Add 32-bit constant address space"Matt Arsenault2018-02-091-1/+2
* AMDGPU: Fix layering issueMatt Arsenault2018-02-091-18/+0
* Revert "AMDGPU: Add 32-bit constant address space"Rafael Espindola2018-02-071-5/+1
* AMDGPU: Add 32-bit constant address spaceMarek Olsak2018-02-071-1/+5
* [AMDGPU][MC] Corrected dst/data size for MIMG opcodes with d16 modifierDmitry Preobrazhensky2018-02-051-0/+4
* [AMDGPU][MC] Added validation of d16 and r128 modifiers of MIMG opcodesDmitry Preobrazhensky2018-02-051-0/+4
* [AMDGPU] Switch to the new addr space mapping by defaultYaxun Liu2018-02-021-11/+3
* [AMDGPU][MC] Added support of 64-bit image atomicsDmitry Preobrazhensky2018-01-261-0/+22
* [AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK supportDmitry Preobrazhensky2018-01-101-0/+4
* [AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registersDmitry Preobrazhensky2017-12-221-0/+4
* AMDGPU: Partially fix disassembly of MIMG instructionsMatt Arsenault2017-12-131-0/+64
* [AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tmaDmitry Preobrazhensky2017-12-111-29/+53
* AMDGPU/GCN: Bring processors in sync with AMDGPUUsageKonstantin Zhuravlyov2017-12-081-10/+7
* AMDGPU: Fix set but not used warnings related to AMDGPUASKonstantin Zhuravlyov2017-11-011-6/+6
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