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| author | Ron Lieberman <ronlieb.g@gmail.com> | 2018-11-16 01:13:34 +0000 |
|---|---|---|
| committer | Ron Lieberman <ronlieb.g@gmail.com> | 2018-11-16 01:13:34 +0000 |
| commit | cac749ac884cfab87a0b2a805b43530c26a627c8 (patch) | |
| tree | 483b52cfd6f80f9842c2ce8132146e9dd1b798e0 /llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | |
| parent | 5d14b72d5c3f5169fd896ce91378e377f464b18b (diff) | |
| download | bcm5719-llvm-cac749ac884cfab87a0b2a805b43530c26a627c8.tar.gz bcm5719-llvm-cac749ac884cfab87a0b2a805b43530c26a627c8.zip | |
[AMDGPU] Add FixupVectorISel pass, currently Supports SREGs in GLOBAL LD/ST
Add a pass to fixup various vector ISel issues.
Currently we handle converting GLOBAL_{LOAD|STORE}_*
and GLOBAL_Atomic_* instructions into their _SADDR variants.
This involves feeding the sreg into the saddr field of the new instruction.
llvm-svn: 347008
Diffstat (limited to 'llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp index fc1e71299c5..c43389a13b8 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -755,6 +755,7 @@ unsigned getRegBitWidth(unsigned RCID) { case AMDGPU::VS_64RegClassID: case AMDGPU::SReg_64RegClassID: case AMDGPU::VReg_64RegClassID: + case AMDGPU::SReg_64_XEXECRegClassID: return 64; case AMDGPU::VReg_96RegClassID: return 96; |
