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path: root/llvm/lib/Target/AMDGPU/SMInstructions.td
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* [AMDGPU] deduplicate tablegen predicatesStanislav Mekhanoshin2019-11-041-5/+5
* AMDGPU/GlobalISel: Select SMRD loads for more typesMatt Arsenault2019-09-161-3/+12
* [AMDGPU] Always use s_memtime for readcyclecounterStanislav Mekhanoshin2019-07-091-11/+0
* AMDGPU/GFX10: Support DLC bit in llvm.amdgcn.s.buffer.load intrinsicNicolai Haehnle2019-06-161-6/+8
* [AMDGPU] gfx1010 VMEM and SMEM implementationStanislav Mekhanoshin2019-04-301-29/+248
* [AMDGPU] Sort out and rename multiple CI/VI predicatesStanislav Mekhanoshin2019-04-061-9/+9
* [AMDGPU] predicate and feature refactoringStanislav Mekhanoshin2019-04-051-13/+13
* AMDGPU: Remove IntrReadMem from memtime/memrealtime intrinsicsMatt Arsenault2019-02-251-2/+10
* Revert "AMDGPU/NFC: Cleanup subtarget predicates"Konstantin Zhuravlyov2019-02-221-14/+14
* AMDGPU/NFC: Cleanup subtarget predicatesKonstantin Zhuravlyov2019-02-211-14/+14
* AMDGPU/GlobalISel: Move SMRD selection logic to TableGenTom Stellard2019-02-201-1/+22
* AMDGPU: Remove GCN features and predicatesMatt Arsenault2019-02-081-1/+0
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* AMDGPU: Allow f32 types for llvm.amdgcn.s.buffer.loadMatt Arsenault2018-12-071-0/+6
* AMDGPU: Consolidate SMRD TableGen patternsTom Stellard2018-10-061-100/+80
* AMDGPU/SI: Change predicate to isCIOnly for 32-bit imm s_buffer_load* patternsTom Stellard2018-09-261-1/+1
* [AMDGPU] Load divergence predicate refactoringAlexander Timofeev2018-09-131-8/+1
* AMDGPU: Remove remnants of old address space mappingMatt Arsenault2018-08-311-2/+2
* [AMDGPU] Add support for multi-dword s.buffer.load intrinsicTim Renouf2018-08-251-16/+32
* [AMDGPU][MC][VI][GFX9] Added s_atc_probe* instructionsDmitry Preobrazhensky2018-04-061-0/+28
* [AMDGPU][MC][GFX9] Added s_dcache_discard* instructionsDmitry Preobrazhensky2018-04-061-0/+30
* [AMDGPU][MC][GFX9] Added s_atomic_* and s_buffer_atomic_* instructionsDmitry Preobrazhensky2018-04-021-0/+188
* Revert r328975, it makes TableGen assert on the bots.Nico Weber2018-04-021-188/+0
* [AMDGPU][MC][GFX9] Added s_atomic_* and s_buffer_atomic_* instructionsDmitry Preobrazhensky2018-04-021-0/+188
* [AMDGPU][MC][GFX9] Added s_scratch* instructionsDmitry Preobrazhensky2018-03-281-0/+15
* TableGen: Check the dynamic type of !cast<Rec>(string)Nicolai Haehnle2018-03-191-1/+1
* Pass Divergence Analysis data to Selection DAG to drive divergenceAlexander Timofeev2018-03-051-5/+2
* Reapply "AMDGPU: Add 32-bit constant address space"Matt Arsenault2018-02-091-1/+2
* Revert "AMDGPU: Add 32-bit constant address space"Rafael Espindola2018-02-071-2/+1
* AMDGPU: Add 32-bit constant address spaceMarek Olsak2018-02-071-1/+2
* AMDGPU: Set IntrReadMem on memtime intrinsicsMatt Arsenault2017-12-081-5/+2
* AMDGPU: Select s_buffer_load_dword with a non-constant SGPR offsetMarek Olsak2017-10-311-2/+1
* AMDGPU: Remove global isGCN predicatesMatt Arsenault2017-10-031-17/+13
* AMDGPUAnnotateUniformValue should always treat volatile loads as divergentAlexander Timofeev2017-06-021-0/+1
* Revert "AMDGPU: Fold CI-specific complex SMRD patterns into existing complex ...Marek Olsak2017-05-241-1/+26
* AMDGPU: Fold CI-specific complex SMRD patterns into existing complex patternsMarek Olsak2017-05-231-26/+1
* [AMDGPU] Get address space mapping by target triple environmentYaxun Liu2017-03-271-2/+2
* AMDGPU: Remove a useless VI SMRD patternMarek Olsak2017-01-301-6/+0
* [AMDGPU] Scalarization of global uniform loads.Alexander Timofeev2016-12-081-2/+6
* [AMDGPU] Disassembler: fix s_buffer_store_dword instructionsSam Kolton2016-12-051-2/+11
* AMDGPU: Disallow exec as SMEM instruction operandMatt Arsenault2016-11-291-9/+14
* [AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM instructions.Artem Tamazov2016-10-311-5/+9
* AMDGPU: Add definitions for scalar store instructionsMatt Arsenault2016-10-281-21/+104
* [AMDGPU] Scalar Memory instructions TD refactoringValery Pykhtin2016-09-011-0/+430
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