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path: root/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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* Use MCRegister in MCRegisterInfo's interfacesDaniel Sanders2019-08-021-3/+3
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders2019-08-011-3/+3
* [AMDGPU] Reserve all AGPRs on targets which do not have themStanislav Mekhanoshin2019-07-301-0/+8
* [AMDGPU] Allow register tuples to set asm namesStanislav Mekhanoshin2019-07-191-14/+1
* [AMDGPU] Drop Reg32 and use regular AsmNameStanislav Mekhanoshin2019-07-181-1/+0
* [AMDGPU] Stop special casing flat_scratch for register nameStanislav Mekhanoshin2019-07-171-12/+0
* [AMDGPU] Autogenerate register asm namesStanislav Mekhanoshin2019-07-161-61/+18
* [AMDGPU] gfx908 agpr spillingStanislav Mekhanoshin2019-07-111-17/+108
* [AMDGPU] gfx908 mfma supportStanislav Mekhanoshin2019-07-111-6/+145
* [AMDGPU] gfx908 mAI instructions, MC partStanislav Mekhanoshin2019-07-091-0/+16
* AMDGPU/GlobalISel: Select G_MERGE_VALUESMatt Arsenault2019-07-091-16/+31
* AMDGPU/GlobalISel: Fix scc->vcc copy handlingMatt Arsenault2019-07-011-2/+2
* AMDGPU: Assert SPAdj is 0Matt Arsenault2019-06-261-0/+2
* AMDGPU/GlobalISel: Select G_TRUNCMatt Arsenault2019-06-241-24/+30
* AMDGPU/GlobalISel: Fix selecting G_IMPLICIT_DEF for s1Matt Arsenault2019-06-241-3/+16
* CodeGen: Introduce a class for registersMatt Arsenault2019-06-241-4/+4
* AMDGPU/GlobalISel: Implement select for G_ICMP and G_SELECTTom Stellard2019-06-171-1/+6
* [AMDGPU] gfx10 conditional registers handlingStanislav Mekhanoshin2019-06-161-1/+28
* AMDGPU: Invert frame index offset interpretationMatt Arsenault2019-06-051-27/+34
* AMDGPU: Disable stack realignment for kernelsMatt Arsenault2019-06-031-0/+13
* [AMDGPU][MC] Added support of SCC, VCCZ and EXECZ operandsDmitry Preobrazhensky2019-06-031-0/+5
* [AMDGPU] gfx1010 VMEM and SMEM implementationStanislav Mekhanoshin2019-04-301-3/+7
* [AMDGPU] gfx1010 sgpr register changesStanislav Mekhanoshin2019-04-241-2/+5
* [AMDGPU] Pre-allocate WWM registers to reduce VGPR pressure.Neil Henning2019-04-011-0/+4
* Reapply "AMDGPU: Scavenge register instead of findUnusedReg"Matt Arsenault2019-03-271-1/+1
* AMDGPU: Enable the scavenger for large framesMatt Arsenault2019-03-271-5/+14
* Revert "AMDGPU: Scavenge register instead of findUnusedReg"Matt Arsenault2019-03-251-1/+1
* [AMDGPU] Added v5i32 and v5f32 register classesTim Renouf2019-03-221-0/+32
* [AMDGPU] Support for v3i32/v3f32Tim Renouf2019-03-211-1/+12
* [AMDGPU][MC][GFX9] Added support of operands shared_base, shared_limit, priva...Dmitry Preobrazhensky2019-03-201-0/+3
* [AMDGPU] Asm/disasm clamp modifier on vop3 int arithmeticTim Renouf2019-03-181-3/+6
* AMDGPU: Scavenge register instead of findUnusedRegMatt Arsenault2019-03-141-1/+1
* AMDGPU/GlobalISel: Implement select for G_EXTRACTTom Stellard2019-02-281-0/+7
* [AMDGPU][MC] Added support of lds_direct operandDmitry Preobrazhensky2019-02-081-0/+3
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [AMDGPU] Simplify negated conditionStanislav Mekhanoshin2018-12-131-0/+57
* AMDGPU: Only add implicit super-reg def for first subregMatt Arsenault2018-11-261-2/+2
* [MI] Change the array of `MachineMemOperand` pointers to beChandler Carruth2018-08-161-9/+10
* [AMDGPU] Fix VGPR spills where offset doesn't fit in 12 bitsScott Linder2018-07-261-11/+16
* AMDGPU: Refactor Subtarget classesTom Stellard2018-07-111-12/+12
* AMDGPU: Separate R600 and GCN TableGen filesTom Stellard2018-06-281-2/+0
* AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headersTom Stellard2018-05-221-0/+6
* AMDGPU/GlobalISel: Implement select() for >32-bit G_STORETom Stellard2018-05-111-0/+6
* AMDGPU/GlobalISel: Enable TableGen'd instruction selectorTom Stellard2018-05-101-0/+21
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-011-2/+2
* AMDGPU: Move a flawed assert when spilling SGPRsMatt Arsenault2018-04-231-0/+4
* [AMDGPU] : fix for the crash in SIRegisterInfo when the regiser class not foundAlexander Timofeev2018-03-011-1/+7
* [AMDGPU] added writelane intrinsicTim Renouf2018-02-281-1/+12
* [AMDGPU] Make sure all super regs of reserved regs are marked reserved.Geoff Berry2018-01-241-7/+0
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-01-221-2/+2
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