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path: root/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
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* [llvm] Migrate llvm::make_unique to std::make_uniqueJonas Devlieghere2019-08-151-3/+3
| | | | | | | | Now that we've moved to C++14, we no longer need the llvm::make_unique implementation from STLExtras.h. This patch is a mechanical replacement of (hopefully) all the llvm::make_unique instances across the monorepo. llvm-svn: 369013
* Delete dead storesFangrui Song2019-07-121-1/+1
| | | | llvm-svn: 365903
* [AMDGPU] gfx1010 memory legalizerStanislav Mekhanoshin2019-05-061-1/+262
| | | | | | Differential Revision: https://reviews.llvm.org/D61535 llvm-svn: 360087
* AMDGPU: Add support for cross address space synchronization scopesKonstantin Zhuravlyov2019-03-251-20/+30
| | | | | | Differential Revision: https://reviews.llvm.org/D59517 llvm-svn: 356946
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [AMDGPU] Change the l1 flush instruction for AMDPAL/MESA3D.Neil Henning2018-12-101-1/+7
| | | | | | | | | | This commit changes which l1 flush instruction is used for AMDPAL and MESA3d workloads to flush the entire l1 cache instead of just the volatile lines. Differential Revision: https://reviews.llvm.org/D55367 llvm-svn: 348771
* AMDGPU: Re-apply r341982 after fixing the layering issueKonstantin Zhuravlyov2018-09-121-2/+2
| | | | | | | | | | | | Move isa version determination into TargetParser. Also switch away from target features to CPU string when determining isa version. This fixes an issue when we output wrong isa version in the object code when features of a particular CPU are altered (i.e. gfx902 w/o xnack used to result in gfx900). llvm-svn: 342069
* Revert "AMDGPU: Move isa version and EF_AMDGPU_MACH_* determination into ↵Ilya Biryukov2018-09-121-2/+2
| | | | | | | | | | | TargetParser." This reverts commit r341982. The change introduced a layering violation. Reverting to unbreak our integrate. llvm-svn: 342023
* AMDGPU: Move isa version and EF_AMDGPU_MACH_* determinationKonstantin Zhuravlyov2018-09-111-2/+2
| | | | | | | | | | | | | | into TargetParser. Also switch away from target features to CPU string when determining isa version. This fixes an issue when we output wrong isa version in the object code when features of a particular CPU are altered (i.e. gfx902 w/o xnack used to result in gfx900). Differential Revision: https://reviews.llvm.org/D51890 llvm-svn: 341982
* AMDGPU: Remove remnants of old address space mappingMatt Arsenault2018-08-311-8/+5
| | | | llvm-svn: 341165
* run post-RA hazard recognizer pass lateMark Searles2018-07-161-1/+1
| | | | | | | | | | | | | Memory legalizer, waitcnt, and shrink passes can perturb the instructions, which means that the post-RA hazard recognizer pass should run after them. Otherwise, one of those passes may invalidate the work done by the hazard recognizer. Note that this has adverse side-effect that any consecutive S_NOP 0's, emitted by the hazard recognizer, will not be shrunk into a single S_NOP <N>. This should be addressed in a follow-on patch. Differential Revision: https://reviews.llvm.org/D49288 llvm-svn: 337154
* AMDGPU: Refactor Subtarget classesTom Stellard2018-07-111-8/+8
| | | | | | | | | | | | | | | | | Summary: This is a follow-up to r335942. - Merge SISubtarget into AMDGPUSubtarget and rename to GCNSubtarget - Rename AMDGPUCommonSubtarget to AMDGPUSubtarget - Merge R600Subtarget::Generation and GCNSubtarget::Generation into AMDGPUSubtarget::Generation. Reviewers: arsenm, jvesely Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D49037 llvm-svn: 336851
* [AMDGPU] Simplify memory legalizer (add missing virtual descructor)Tony Tye2018-06-081-0/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D47504 llvm-svn: 334257
* [AMDGPU] Simplify memory legalizerTony Tye2018-06-071-234/+707
| | | | | | | | | | - Make code easier to maintain. - Avoid generating waitcnts for VMEM if the address sppace does not involve VMEM. - Add support to generate waitcnts for LDS and GDS memory. Differential Revision: https://reviews.llvm.org/D47504 llvm-svn: 334241
* AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headersTom Stellard2018-05-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: MCTargetDesc/AMDGPUMCTargetDesc.h contains enums for all the instuction and register defintions, which are huge so we only want to include them where needed. This will also make it easier if we want to split the R600 and GCN definitions into separate tablegenerated files. I was unable to remove AMDGPUMCTargetDesc.h from SIMachineFunctionInfo.h because it uses some enums from the header to initialize default values for the SIMachineFunction class, so I ended up having to remove includes of SIMachineFunctionInfo.h from headers too. Reviewers: arsenm, nhaehnle Reviewed By: nhaehnle Subscribers: MatzeB, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D46272 llvm-svn: 332930
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-011-17/+17
| | | | | | | | | | | | | | | | We've been running doxygen with the autobrief option for a couple of years now. This makes the \brief markers into our comments redundant. Since they are a visual distraction and we don't want to encourage more \brief markers in new code either, this patch removes them all. Patch produced by for i in $(git grep -l '\\brief'); do perl -pi -e 's/\\brief //g' $i & done Differential Revision: https://reviews.llvm.org/D46290 llvm-svn: 331272
* [AMDGPU] More descriptive names in the memory legalizerStanislav Mekhanoshin2018-02-091-19/+20
| | | | | | | | NFC. Differential Revision: https://reviews.llvm.org/D43054 llvm-svn: 324712
* [AMDGPU] removed dead code handling rmw in memory legalizerStanislav Mekhanoshin2018-02-061-66/+3
| | | | | | | | | It was always using cmpxchg path and in rmw and cmpxchg instructions are not distinguishable in the BE. Differential Revision: https://reviews.llvm.org/D42976 llvm-svn: 324383
* AMDGPU/MemoryModel: Fix monotonic atomic loadsKonstantin Zhuravlyov2018-02-061-1/+2
| | | | | | Those should have glc bit set for system and agent synchronization scopes llvm-svn: 324314
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-2/+2
| | | | | | The Function can never be nullptr so we can return a reference. llvm-svn: 320884
* AMDGPU: Handle non-temporal loads and storesKonstantin Zhuravlyov2017-09-071-23/+59
| | | | | | Differential Revision: https://reviews.llvm.org/D36862 llvm-svn: 312729
* AMDGPU: Handle more than one memory operand in SIMemoryLegalizerKonstantin Zhuravlyov2017-09-071-58/+105
| | | | | | Differential Revision: https://reviews.llvm.org/D37397 llvm-svn: 312725
* AMDGPU: Cleanup/refactor SIMemoryLegalizer [3]:Konstantin Zhuravlyov2017-09-051-143/+157
| | | | | | | | | - Refactor SIMemOpInfo's constructors - Allow construction of NotAtomic SIMemOpInfo Differential Revision: https://reviews.llvm.org/D37396 llvm-svn: 312563
* AMDGPU/NFC: Cleanup/refactor SIMemoryLegalizer [2]:Konstantin Zhuravlyov2017-09-051-151/+174
| | | | | | | | | | - Make SIMemOpInfo a class - Add accessor methods to SIMemOpInfo - Move get*Info methods to SIMemOpInfo Differential Revision: https://reviews.llvm.org/D37395 llvm-svn: 312541
* AMDGPU/NFC: Cleanup/refactor SIMemoryLegalizer [1]:Konstantin Zhuravlyov2017-09-051-46/+50
| | | | | | | | | - Rename MemOpInfo -> SIMemOpInfo - Move SIMemOpInfo class out of SIMemoryLegalizer class Differential Revision: https://reviews.llvm.org/D37394 llvm-svn: 312540
* AMDGPU/NFC: Reorder functions in SIMemoryLegalizer:Konstantin Zhuravlyov2017-08-191-52/+52
| | | | | | | - Move *load* functions before *atomic* functions - Move *store* functions before *atomic* functions llvm-svn: 311256
* AMDGPU/NFC: Rename few things in SIMemoryLegalizer:Konstantin Zhuravlyov2017-08-181-113/+107
| | | | | | | | | | | | - AtomicInfo -> MemOpInfo - getAtomicLoadInfo -> getLoadInfo - getAtomicStoreInfo -> getStoreInfo - expandAtomicLoad -> expandLoad - expandAtomicStore -> expandStore Differential Revision: https://reviews.llvm.org/D36861 llvm-svn: 311179
* [AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-08-101-5/+23
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 310541
* AMDGPU: Implement memory modelKonstantin Zhuravlyov2017-07-211-0/+491
llvm-svn: 308781
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