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path: root/llvm/lib/Target/AMDGPU/SIInstrInfo.h
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* Add missing override.Rafael Espindola2016-04-301-1/+2
* AMDGPU/SI: Enable the post-ra schedulerTom Stellard2016-04-301-0/+21
* [MachineScheduler]Add support for store clusteringJun Bum Lim2016-04-151-3/+3
* AMDGPU/SI: Add MachineBasicBlock parameter to SIInstrInfo::insertWaitStatesTom Stellard2016-04-071-1/+2
* AMDGPU: Add SIWholeQuadMode passNicolai Haehnle2016-03-211-0/+4
* AMDGPU/SI: Handle wait states required for DPP instructionsTom Stellard2016-03-141-0/+8
* AMDGPU: R600 code splitting cleanupMatt Arsenault2016-03-111-3/+3
* [TII] Allow getMemOpBaseRegImmOfs() to accept negative offsets. NFC.Chad Rosier2016-03-091-1/+1
* AMDGPU/SI: Use v_readfirstlane to legalize SMRD with VGPR base pointerTom Stellard2016-02-201-9/+2
* AMDGPU/SI: Detect uniform branches and emit s_cbranch instructionsTom Stellard2016-02-121-0/+3
* AMDGPU: Set element_size in private resource descriptorMatt Arsenault2016-02-121-1/+1
* AMDGPU/SI: Make sure MIMG descriptors and samplers stay in SGPRsTom Stellard2016-02-111-0/+7
* AMDGPU: Remove some purely R600 functions from AMDGPUInstrInfoTom Stellard2016-02-051-14/+0
* AMDGPU: Move subtarget specific code out of AMDGPUInstrInfo.cppTom Stellard2016-01-281-5/+10
* AMDGPU/SI: Add SI Machine SchedulerNicolai Haehnle2016-01-131-0/+3
* AMDGPU: Fix off-by-one in SIRegisterInfo::eliminateFrameIndexNicolai Haehnle2015-12-171-1/+1
* AMDGPU: Optimize VOP2 operand legalizationMatt Arsenault2015-12-011-0/+17
* AMDGPU/SI: select S_ABS_I32 when possible (v2)Marek Olsak2015-11-251-0/+3
* AMDGPU: Fix assert when legalizing atomic operandsMatt Arsenault2015-11-051-0/+6
* AMDGPU: Simplify VOP3 operand legalization.Matt Arsenault2015-10-211-0/+3
* AMDGPU: Add MachineInstr overloads for instruction format testsMatt Arsenault2015-10-201-0/+76
* AMDGPU/SI: Don't set DATA_FORMAT if ADD_TID_ENABLE is setMarek Olsak2015-09-291-1/+1
* AMDGPU: Factor switch into separate functionMatt Arsenault2015-09-281-0/+3
* Improved the interface of methods commuting operands, improved X86-FMA3 mem-f...Andrew Kaylor2015-09-281-2/+6
* AMDGPU: Construct new buffer instruction when moving SMRDMatt Arsenault2015-09-251-1/+2
* AMDGPU: Make getNamedOperandIdx declaration readonlyMatt Arsenault2015-09-251-0/+2
* AMDGPU: Add readonly to InstrMapping functionsMatt Arsenault2015-09-241-1/+15
* AMDGPU: Delete dead codeMatt Arsenault2015-08-261-6/+0
* AMDGPU: Don't create intermediate SALU instructionsMatt Arsenault2015-08-261-0/+4
* AMDGPU/SI: Remove EXECRegMatt Arsenault2015-08-051-2/+0
* AMDGPU/SI: Add implicit register operands in the correct order.Alex Lorenz2015-07-311-2/+0
* AMDGPU/SI: Remove isTriviallyReMaterializable() function from SIInstrInfoTom Stellard2015-07-301-3/+0
* AMDGPU/SI: Select mad patterns to v_mac_f32Tom Stellard2015-07-131-0/+4
* AMDGPU: really don't commute REV opcodes if the target variant doesn't existMarek Olsak2015-06-261-1/+1
* [TargetInstrInfo] Rename getLdStBaseRegImmOfs and implement for x86.Sanjoy Das2015-06-151-3/+3
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+391
* Revert "AMDGPU: Add core backend files for R600/SI codegen v6"Tom Stellard2012-07-161-89/+0
* AMDGPU: Add core backend files for R600/SI codegen v6Tom Stellard2012-07-161-0/+89
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