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path: root/llvm/lib/Target/AMDGPU/SIISelLowering.h
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* CodeGen: Use LLT instead of EVT in getRegisterByNameMatt Arsenault2020-01-091-1/+1
* AMDGPU: Refactor treatment of denormal modeMatt Arsenault2019-11-191-1/+1
* DAG: Add function context to isFMAFasterThanFMulAndFAddMatt Arsenault2019-11-191-1/+2
* DAG: Add DAG argument to isFPExtFoldableMatt Arsenault2019-10-311-1/+2
* DAG: Add new control for ISD::FMAD formationMatt Arsenault2019-10-311-0/+3
* AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHGMatt Arsenault2019-10-251-0/+8
* [AMDGPU] Come back patch for the 'Assign register class for cross block value...Alexander Timofeev2019-10-141-0/+4
* AMDGPU: Add offsets to MMO when lowering buffer intrinsicsTom Stellard2019-10-081-2/+4
* TLI: Remove DAG argument from getRegisterByNameMatt Arsenault2019-10-011-2/+2
* AMDGPU/GlobalISel: Legalize G_GLOBAL_VALUEMatt Arsenault2019-10-011-0/+2
* [Alignment][NFC] Remove unneeded llvm:: scoping on Align typesGuillaume Chatelet2019-09-271-1/+1
* AMDGPU/GlobalISel: First pass at attempting to legalize load/storesMatt Arsenault2019-09-101-0/+5
* [Alignment][NFC] Use llvm::Align for TargetLowering::getPrefLoopAlignmentGuillaume Chatelet2019-09-101-1/+1
* [LLVM][Alignment] Make functions using log of alignment explicitGuillaume Chatelet2019-09-051-2/+1
* AMDGPU: Correct behavior of f16 buffer loadsMatt Arsenault2019-08-051-0/+3
* [AMDGPU] Enable v4f16 and above for v_pk_fma instructionsDavid Stuttard2019-07-291-0/+1
* AMDGPU: Force s_waitcnt after GWS instructionsMatt Arsenault2019-07-191-0/+1
* AMDGPU/GlobalISel: Rewrite lowerFormalArgumentsMatt Arsenault2019-07-191-0/+27
* [AMDGPU] Custom lower INSERT_SUBVECTOR v3, v4, v5, v8Tim Renouf2019-07-041-0/+1
* AMDGPU: Custom lower vector_shuffle for v4i16/v4f16Matt Arsenault2019-07-021-0/+1
* AMDGPU: Insert mem_viol check loop around GWS pre-GFX9Matt Arsenault2019-06-201-0/+3
* AMDGPU/GFX10: Support DLC bit in llvm.amdgcn.s.buffer.load intrinsicNicolai Haehnle2019-06-161-1/+1
* [TargetLowering] Add MachineMemOperand::Flags to allowsMemoryAccess tests (PR...Simon Pilgrim2019-06-121-3/+4
* [AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fddAlexander Timofeev2019-06-061-4/+1
* TTI: Improve default costs for addrspacecastMatt Arsenault2019-06-031-1/+1
* AMDGPU: Return address loweringAakanksha Patil2019-05-291-1/+1
* [AMDGPU] Divergence driven ISel. Assign register class for cross block va...Alexander Timofeev2019-05-261-1/+4
* Revert r361644, "[AMDGPU] Divergence driven ISel. Assign register class for c...Peter Collingbourne2019-05-251-4/+1
* [AMDGPU] Divergence driven ISel. Assign register class for cross block values...Alexander Timofeev2019-05-241-1/+4
* [AMDGPU] gfx1010 loop alignmentStanislav Mekhanoshin2019-05-031-0/+2
* [TargetLowering] Change getOptimalMemOpType to take a function attribute listSjoerd Meijer2019-04-301-1/+1
* [AMDGPU] Implemented dwordx3 variants of buffer/tbuffer load/store intrinsicsTim Renouf2019-03-221-0/+6
* [AMDGPU] Add buffer/load 8/16 bit overloaded intrinsicsRyan Taylor2019-03-191-0/+10
* AMDGPU: Remove debugger related subtarget featuresMatt Arsenault2019-02-211-2/+0
* [AMDGPU] Ressociate 'add (add x, y), z' to use SALUStanislav Mekhanoshin2019-02-141-0/+1
* Codegen support for atomicrmw fadd/fsubMatt Arsenault2019-01-221-0/+1
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [AMDGPU] Promote constant offset to the immediate by finding a new base with ...Farhana Aleen2018-12-141-1/+1
* AMDGPU: Divergence-driven selection of scalar buffer load intrinsicsNicolai Haehnle2018-11-301-1/+3
* [AMDGPU] Convert insert_vector_elt into set of selectsStanislav Mekhanoshin2018-11-191-0/+1
* Revert "AMDGPU: Divergence-driven selection of scalar buffer load intrinsics"Nicolai Haehnle2018-11-071-3/+1
* [TargetLowering] Change TargetLoweringBase::getPreferredVectorAction to take ...Craig Topper2018-11-051-1/+1
* AMDGPU: Remove custom BUILD_VECTOR combineMatt Arsenault2018-10-301-1/+0
* DAG: Change behavior of fminnum/fmaxnum nodesMatt Arsenault2018-10-221-0/+6
* AMDGPU: Divergence-driven selection of scalar buffer load intrinsicsNicolai Haehnle2018-10-171-1/+3
* [NFC] Rename the DivergenceAnalysis to LegacyDivergenceAnalysisNicolai Haehnle2018-08-301-1/+1
* AMDGPU: Fix not respecting byval alignment in call frame setupMatt Arsenault2018-08-221-2/+2
* [AMDGPU] New buffer intrinsicsTim Renouf2018-08-211-0/+6
* [AMDGPU] New tbuffer intrinsicsTim Renouf2018-08-211-0/+9
* AMDGPU: Refactor fcanonicalize combineMatt Arsenault2018-08-061-0/+2
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