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path: root/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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* AMDGPU: Cleanup CreateLiveInRegisterMatt Arsenault2017-06-191-9/+0
* AMDGPU: Teach isLegalAddressingMode about flat offsetsMatt Arsenault2017-06-121-3/+11
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-2/+2
* [llvm] Remove double semicolonsMandeep Singh Grang2017-06-061-1/+1
* AMDGPUAnnotateUniformValue should always treat volatile loads as divergentAlexander Timofeev2017-06-021-1/+1
* [AMDGPU] Prevent too large store merges in AMDGPU Subtargets. NFCI.Nirav Dave2017-05-241-0/+12
* [AMDGPU] Combine and (srl) into shl (bfe)Stanislav Mekhanoshin2017-05-231-6/+34
* AMDGPU: Start defining a calling conventionMatt Arsenault2017-05-171-15/+150
* AMDGPU: Make better use of op_sel with high componentsMatt Arsenault2017-05-171-0/+9
* AMDGPU: Fix min3/max3 combines for f16/i16Matt Arsenault2017-05-171-1/+2
* [AMDGPU] Placate unused variable warning in release builds.Davide Italiano2017-05-111-0/+1
* AMDGPU: Pull fneg out of extract_vector_eltMatt Arsenault2017-05-111-0/+21
* AMDGPU: GFX9 GS and HS shaders always have the scratch wave offset in SGPR5Marek Olsak2017-05-041-3/+11
* Generalize the specialized flag-carrying SDNodes by moving flags into SDNode.Amara Emerson2017-05-011-9/+8
* AMDGPU: Add new amdgcn.init.exec intrinsicsMarek Olsak2017-04-281-0/+65
* [SelectionDAG] Use KnownBits struct in DAG's computeKnownBits and simplifyDem...Craig Topper2017-04-281-2/+3
* Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-10/+11
* AMDGPU: Move trap lowering to DAGMatt Arsenault2017-04-241-46/+57
* AMDGPU: Do not lower fast unsafe div for safe, f32, with fp32 denormalsKonstantin Zhuravlyov2017-04-211-2/+4
* [AArch64] Improve code generation for logical instructions takingAkira Hatanaka2017-04-211-1/+1
* Revert r300932 and r300930.Akira Hatanaka2017-04-211-1/+1
* [AArch64] Improve code generation for logical instructions takingAkira Hatanaka2017-04-211-1/+1
* AMDGPU: Custom lower illegal small select typesMatt Arsenault2017-04-191-0/+29
* AMDGPU: Fix invalid copies when copying i1 to phys regMatt Arsenault2017-04-121-2/+28
* AMDGPU: Refactor SIMachineFunctionInfo slightlyMatt Arsenault2017-04-111-1/+1
* AMDGPU: Refactor argument loweringMatt Arsenault2017-04-111-256/+318
* AMDGPU/GFX9: Fix shared and private aperture queriesKonstantin Zhuravlyov2017-04-061-11/+23
* AMDGPU: Replace fp16SrcZerosHighBits with a whitelistMatt Arsenault2017-04-061-4/+50
* AMDGPU: Stop using CCAssignToRegWithShadowMatt Arsenault2017-04-061-11/+0
* [AMDGPU] Eliminate barrier if workgroup size is not greater than wavefront sizeStanislav Mekhanoshin2017-04-061-0/+11
* AMDGPU: Remove legacy export intrinsicMatt Arsenault2017-04-041-23/+0
* AMDGPU: Remove llvm.SI.vs.load.inputMatt Arsenault2017-04-031-5/+0
* AMDGPU: Remove legacy bfe intrinsicsMatt Arsenault2017-04-031-3/+7
* AMDGPU: Remove unnecessary ands when f16 is legalMatt Arsenault2017-03-311-0/+39
* AMDGPU: Add all atomicrmw fields to atomic.inc/decMatt Arsenault2017-03-301-2/+5
* [AMDGPU] Get address space mapping by target triple environmentYaxun Liu2017-03-271-75/+72
* AMDGPU: Implement f16 froundMatt Arsenault2017-03-241-0/+1
* AMDGPU: Rename SI_RETURNMatt Arsenault2017-03-211-1/+1
* AMDGPU: Always use VGPR indexing on GFX9Marek Olsak2017-03-211-2/+2
* AMDGPU: Fix asserting on 0 dmask for image intrinsicsMatt Arsenault2017-03-211-0/+58
* AMDGPU: Cleanup control flow intrinsicsMatt Arsenault2017-03-171-25/+18
* AMDGPU: Allow sinking of addressing modes for atomic_inc/decMatt Arsenault2017-03-151-5/+22
* AMDGPU: Re-use TM.getNullPointerValueMatt Arsenault2017-03-131-10/+8
* AMDGPU: Treat 0 as private null pointer in addrspacecast loweringMatt Arsenault2017-03-131-7/+14
* AMDGPU: Remove packf16 intrinsicMatt Arsenault2017-03-111-5/+0
* AMDGPU: Use v_med3_{f16|i16|u16}Matt Arsenault2017-02-271-17/+16
* AMDGPU: Support v2i16/v2f16 packed operationsMatt Arsenault2017-02-271-6/+69
* AMDGPU: Support inlineasm for packed instructionsMatt Arsenault2017-02-271-1/+42
* AMDGPU: Use clamp with f64Matt Arsenault2017-02-221-5/+8
* AMDGPU : Update TrapCode based on Trap Handler ABI.Wei Ding2017-02-221-2/+2
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