summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/AMDGPU/SIDefines.h
Commit message (Expand)AuthorAgeFilesLines
* [AMDGPU] Added MI bit IsDOTStanislav Mekhanoshin2019-09-171-1/+4
* [AMDGPU] gfx10 atomic optimizer changes.Jay Foad2019-08-231-0/+1
* [AMDGPU][MC][GFX9][GFX10] Added support of GET_DOORBELL messageDmitry Preobrazhensky2019-07-151-0/+1
* [AMDGPU] gfx908 mAI instructions, MC partStanislav Mekhanoshin2019-07-091-1/+4
* [AMDGPU] gfx908 register file changesStanislav Mekhanoshin2019-07-091-1/+12
* [AMDGPU][MC] Enabled constant expressions as operands of sendmsgDmitry Preobrazhensky2019-06-281-6/+7
* [AMDGPU] hazard recognizer for fp atomic to s_denorm_modeStanislav Mekhanoshin2019-06-211-1/+4
* AMDGPU: Insert mem_viol check loop around GWS pre-GFX9Matt Arsenault2019-06-201-0/+2
* Describe stack-id as an enumSander de Smalen2019-06-171-7/+0
* [AMDGPU][MC] Enabled constant expressions as operands of s_getreg/s_setregDmitry Preobrazhensky2019-06-131-0/+5
* [AMDGPU] gfx1010 dpp16 and dpp8Stanislav Mekhanoshin2019-06-121-1/+14
* [AMDGPU] gfx1010 utility functionsStanislav Mekhanoshin2019-04-251-1/+3
* [AMDGPU] gfx1010 sgpr register changesStanislav Mekhanoshin2019-04-241-5/+17
* [AMDGPU] Add gfx1010 target definitionsStanislav Mekhanoshin2019-04-241-0/+18
* [AMDGPU] predicate and feature refactoringStanislav Mekhanoshin2019-04-051-1/+4
* [AMDGPU] Mark enum types in SIDefines.h as unsignedStanislav Mekhanoshin2019-03-111-17/+17
* [AMDGPU][MC][GFX8+] Added syntactic sugar for 'vgpr index' operand of instruc...Dmitry Preobrazhensky2019-02-271-7/+23
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [AMDGPU] Add new Mode Register passTim Corringham2018-12-101-1/+4
* AMDGPU: Turn D16 for MIMG instructions into a regular operandNicolai Haehnle2018-06-211-2/+2
* [AMDGPU] Added checks for dpp_ctrl valueStanislav Mekhanoshin2018-05-081-0/+38
* AMDGPU: Assign enum name to stack IDMatt Arsenault2018-04-231-0/+7
* AMDGPU/SI: Add d16 support for image intrinsics.Changpeng Fang2018-01-181-1/+4
* [AMDGPU][MC][GFX9] Enable inline constants for SDWA operandsDmitry Preobrazhensky2018-01-171-1/+0
* [AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32Stanislav Mekhanoshin2018-01-151-1/+2
* [AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tmaDmitry Preobrazhensky2017-12-111-2/+6
* [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/su...Dmitry Preobrazhensky2017-11-201-1/+1
* [AMDGPU][MC][GFX9][disassembler] Corrected decoding of op_sel_hi for v_mad_mix*Dmitry Preobrazhensky2017-11-171-1/+4
* [AMDGPU] calling conventions for AMDPAL OS typeTim Renouf2017-09-291-0/+2
* AMDGPU: Fold clamp modifier for packed instructionsMatt Arsenault2017-08-311-5/+16
* [AMDGPU][MC][GFX9] Added integer clamping support for VOP3 opcodesDmitry Preobrazhensky2017-08-161-1/+2
* [AMDGPU][MC][GFX9] Added 16-bit renamed and "_legacy" VALU opcodesDmitry Preobrazhensky2017-08-091-1/+2
* AMDGPU: Introduce maybeAtomic instruction flagKonstantin Zhuravlyov2017-07-211-1/+2
* [AMDGPU][MC][GFX9] Added support of VOP3 'op_sel' modifierDmitry Preobrazhensky2017-07-211-2/+4
* [AMDGPU] SDWA: merge VI and GFX9 pseudo instructionsSam Kolton2017-06-211-3/+3
* [AMDGPU][MC] New syntax for ds_swizzle_b32 offsetDmitry Preobrazhensky2017-05-311-0/+40
* [AMDGPU] SDWA: add disassembler support for GFX9Sam Kolton2017-05-261-4/+11
* [AMDGPU] SDWA: Add assembler support for GFX9Sam Kolton2017-05-231-1/+11
* AMDGPU: Add AMDGPU_HS calling conventionMarek Olsak2017-05-021-0/+1
* AMDGPU/GFX9: Fix shared and private aperture queriesKonstantin Zhuravlyov2017-04-061-2/+9
* AMDGPU: Add VOP3P instruction formatMatt Arsenault2017-02-271-4/+10
* AMDGPU: Fold FP clamp as modifier bitMatt Arsenault2017-02-221-2/+2
* AMDGPU : Add trap handler support.Wei Ding2017-02-101-1/+3
* AMDGPU: Fix handling of 16-bit immediatesMatt Arsenault2016-12-101-5/+24
* AMDGPU: Clean up instruction bitsMatt Arsenault2016-12-091-56/+62
* AMDGPU: Refactor exp instructionsMatt Arsenault2016-12-051-10/+11
* AMDGPU: Workaround for instruction size with literalsMatt Arsenault2016-11-011-1/+2
* AMDGPU: Add definitions for scalar store instructionsMatt Arsenault2016-10-281-1/+2
* AMDGPU/SI: Handle hazard with s_rfe_b64Tom Stellard2016-10-271-0/+7
* AMDGPU: Add instruction definitions for VGPR indexingMatt Arsenault2016-10-121-0/+9
OpenPOWER on IntegriCloud