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path: root/llvm/lib/Target/AMDGPU/MIMGInstructions.td
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* [AMDGPU] deduplicate tablegen predicatesStanislav Mekhanoshin2019-11-041-5/+5
* [AMDGPU] Use PredicateControl in MIMGBaseOpcode. NFC.Stanislav Mekhanoshin2019-08-121-2/+2
* [AMDGPU] Extend MIMG opcode to 8 bitsStanislav Mekhanoshin2019-07-121-20/+25
* [AMDGPU] hazard recognizer for fp atomic to s_denorm_modeStanislav Mekhanoshin2019-06-211-0/+2
* [AMDGPU] Optimize image_[load|store]_mipPiotr Sobczak2019-06-101-0/+20
* [AMDGPU] gfx1010 MIMG implementationStanislav Mekhanoshin2019-05-011-86/+315
* [AMDGPU] Sort out and rename multiple CI/VI predicatesStanislav Mekhanoshin2019-04-061-2/+2
* [AMDGPU] predicate and feature refactoringStanislav Mekhanoshin2019-04-051-2/+2
* [AMDGPU] Use three- and five-dword result type in image opsTim Renouf2019-03-221-6/+6
* Revert "AMDGPU/NFC: Cleanup subtarget predicates"Konstantin Zhuravlyov2019-02-221-2/+2
* AMDGPU/NFC: Cleanup subtarget predicatesKonstantin Zhuravlyov2019-02-211-2/+2
* AMDGPU: Remove GCN features and predicatesMatt Arsenault2019-02-081-1/+0
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [AMDGPU] Add support for TFE/LWE in image intrinsics. 2nd tryDavid Stuttard2019-01-141-1/+9
* Revert r347871 "Fix: Add support for TFE/LWE in image intrinsic"David Stuttard2018-11-291-9/+1
* Add support for TFE/LWE in image intrinsicsDavid Stuttard2018-11-291-1/+9
* [AMDGPU] Add support for a16 modifiear for gfx9Ryan Taylor2018-08-281-4/+4
* [AMDGPU] Optimize _L image intrinsic to _LZ when lod is zeroRyan Taylor2018-08-011-0/+26
* AMDGPU: Remove redundant MIMG instruction variantsNicolai Haehnle2018-06-211-20/+67
* AMDGPU: Remove old-style image intrinsicsNicolai Haehnle2018-06-211-390/+1
* AMDGPU: Select MIMG instructions manually in SITargetLoweringNicolai Haehnle2018-06-211-178/+44
* AMDGPU: Refactor MIMG instruction TableGen using generic tablesNicolai Haehnle2018-06-211-242/+269
* AMDGPU: Pass AMDGPUSampleVariant to MIMG_{Sampler,Gather}(_WQM)Nicolai Haehnle2018-06-211-69/+73
* AMDGPU: Turn D16 for MIMG instructions into a regular operandNicolai Haehnle2018-06-211-346/+228
* AMDGPU: Make v4i16/v4f16 legalMatt Arsenault2018-06-151-24/+9
* AMDGPU: Make various NamedOperands upper caseNicolai Haehnle2018-06-041-10/+10
* TableGen: Streamline the semantics of NAMENicolai Haehnle2018-06-041-6/+6
* AMDGPU: Make v2i16/v2f16 legal on VIMatt Arsenault2018-05-221-8/+5
* [AMDGPU][MC] Added support of 3-element addresses for MIMG instructionsDmitry Preobrazhensky2018-04-041-1/+9
* AMDGPU: Dimension-aware image intrinsicsNicolai Haehnle2018-04-041-0/+195
* [AMDGPU][MC] Added PCK variants of image load/store instructionsDmitry Preobrazhensky2018-03-281-26/+40
* [AMDGPU][MC] Corrected GATHER4 opcodesDmitry Preobrazhensky2018-03-121-78/+85
* [AMDGPU][MC] Added support of 64-bit image atomicsDmitry Preobrazhensky2018-01-261-14/+40
* [AMDGPU][MC] Enabled disassembler for image atomic operationsDmitry Preobrazhensky2018-01-261-12/+16
* AMDGPU/SI: Add d16 support for image intrinsics.Changpeng Fang2018-01-181-177/+380
* AMDGPU: Remove mayLoad/hasSideEffects from MIMG storesMatt Arsenault2017-12-291-5/+5
* AMDGPU: Partially fix disassembly of MIMG instructionsMatt Arsenault2017-12-131-4/+5
* AMDGPU: image_getlod and image_getresinfo do not read memoryMatt Arsenault2017-12-081-0/+8
* AMDGPU: Remove global isGCN predicatesMatt Arsenault2017-10-031-13/+13
* [AMDGPU] Fix latency of MIMG instructionsMarek Olsak2017-07-041-0/+1
* AMDGPU: Remove legacy image intrinsicsMatt Arsenault2017-04-041-100/+0
* AMDGPU/SI: Add a MachineMemOperand to MIMG instructionsTom Stellard2016-12-201-0/+1
* [AMDGPU] TableGen: change individual instruction flags to bit type from bits<1>Sam Kolton2016-11-151-6/+6
* AMDGPU/SI: Support data types other than V4f32 in image intrinsicsChangpeng Fang2016-11-141-61/+68
* AMDGPU: Rename glc operand typeMatt Arsenault2016-10-281-5/+5
* AMDGPU/SI: Change mimg intrinsic signaturesTom Stellard2016-10-121-18/+23
* AMDGPU/SI: MIMG TD Refactoring.Changpeng Fang2016-09-011-0/+750
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