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path: root/llvm/lib/Target/AMDGPU/InstPrinter
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* [AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registersDmitry Preobrazhensky2017-12-221-2/+2
* [AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tmaDmitry Preobrazhensky2017-12-111-10/+0
* [AMDGPU][MC][DISASSEMBLER][GFX9] Corrected decoding of GLOBAL/SCRATCH opcodesDmitry Preobrazhensky2017-11-272-4/+4
* [AMDGPU][MC][GFX9][disassembler] Corrected decoding of op_sel_hi for v_mad_mix*Dmitry Preobrazhensky2017-11-171-3/+6
* AMDGPU: Add R600InstPrinter classTom Stellard2017-08-172-108/+250
* [AMDGPU][MC] Corrected VOP3 version of v_interp_* instructions for VIDmitry Preobrazhensky2017-08-072-0/+9
* AMDGPU: Remove deadcode from AMDGPUInstPrinterTom Stellard2017-07-292-25/+0
* AMDGPU: Fix allocating pseudo-registersMatt Arsenault2017-07-241-0/+5
* [AMDGPU][MC][GFX9] Added support of VOP3 'op_sel' modifierDmitry Preobrazhensky2017-07-212-4/+21
* [AMDGPU] Add intrinsics for tbuffer load and storeDavid Stuttard2017-06-222-0/+22
* [AMDGPU][MC][GFX9] Corrected VOP3P relevant code to fix disassembler failuresDmitry Preobrazhensky2017-06-211-1/+0
* AMDGPU: Start adding global_* instructionsMatt Arsenault2017-06-202-0/+19
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
* [AMDGPU][MC] New syntax for ds_swizzle_b32 offsetDmitry Preobrazhensky2017-05-312-0/+108
* [AMDGPU][MC] Fix for Bug 28211 + LIT testsDmitry Preobrazhensky2017-04-071-1/+1
* [AMDGPU][MC] Fix for Bugs 28200, 28202 + LIT testsDmitry Preobrazhensky2017-03-201-2/+23
* AMDGPU: Add VOP3P instruction formatMatt Arsenault2017-02-272-0/+87
* AMDGPU: Change exp with compr bit printingMatt Arsenault2017-02-221-3/+11
* [AMDGPU] Add target information that is required by tools to metadataKonstantin Zhuravlyov2017-02-081-5/+6
* AMDGPU: Change vintrp printingMatt Arsenault2016-12-142-0/+19
* [AMDGPU, PowerPC, TableGen] Fix some Clang-tidy modernize and Include What Yo...Eugene Zelenko2016-12-121-5/+4
* AMDGPU: Fix handling of 16-bit immediatesMatt Arsenault2016-12-102-14/+71
* AMDGPU: Change vintrp printing to better match scMatt Arsenault2016-12-101-9/+12
* AMDGPU: Change how exp is printedMatt Arsenault2016-12-052-4/+101
* AMDGPU: Fix formatting of 1/2pi immediateMatt Arsenault2016-11-151-2/+2
* [AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM instructions.Artem Tamazov2016-10-312-2/+10
* AMDGPU: Use 1/2pi inline imm on VIMatt Arsenault2016-10-292-9/+21
* [AMDGPU] Stop using MCRegisterClass::getSize()Krzysztof Parzyszek2016-10-191-7/+7
* AMDGPU: Add instruction definitions for VGPR indexingMatt Arsenault2016-10-122-3/+29
* [AMDGPU] Refactor waitcnt encodingKonstantin Zhuravlyov2016-10-111-6/+5
* [AMDGPU] Assembler: support v_mac_f32 DPP and SDWA. Move getNamedOperandIdx t...Sam Kolton2016-10-071-10/+14
* [AMDGPU] Choose VMCNT, EXPCNT, LGKMCNT masks and shifts based on the isa versionKonstantin Zhuravlyov2016-09-301-4/+9
* [AMDGPU] Enable changing instprinter's behavior based on the per-functionKonstantin Zhuravlyov2016-09-272-132/+209
* AMDGPU] Assembler: better support for immediate literals in assembler.Sam Kolton2016-09-091-1/+1
* [AMDGPU] fix failure on printing of non-existing instruction operands.Valery Pykhtin2016-08-151-0/+5
* Revert "[AMDGPU] fix failure on printing of non-existing instruction operands."Valery Pykhtin2016-08-111-5/+0
* [AMDGPU] fix failure on printing of non-existing instruction operands.Valery Pykhtin2016-08-111-0/+5
* AMDGPU: Remove unnecessary string usage in AsmPrinterMatt Arsenault2016-07-052-38/+49
* [AMDGPU] AsmParser: Support for sext() modifier in SDWA. Some code cleaning i...Sam Kolton2016-06-102-3/+16
* [AMDGPU][llvm-mc] s_getreg/setreg* - hwreg - factor out strings/literals etc.Artem Tamazov2016-05-263-63/+15
* AMDGPU: Add support for MCExpr to instruction printerJan Vesely2016-05-132-3/+10
* [AMDGPU][llvm-mc] Add support for sendmsg(...) syntax.Artem Tamazov2016-05-061-26/+83
* Fixed/Recommitted r267733 "[AMDGPU][llvm-mc] Add support of TTMP quads. Rewor...Artem Tamazov2016-04-291-1/+4
* AMDGPU/SI: Assembler: Unify parsing/printing of operands.Nikolay Haustov2016-04-292-14/+26
* Revert "[AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for ...Chad Rosier2016-04-271-4/+1
* [AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for SMRD.Artem Tamazov2016-04-271-1/+4
* [AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware regis...Artem Tamazov2016-04-271-4/+14
* [AMDGPU] Assembler: basic support for SDWA instructionsSam Kolton2016-04-262-0/+52
* [AMDGPU][llvm-mc] s_getreg/setreg* - Add hwreg(...) syntax.Artem Tamazov2016-04-252-0/+15
* [AMDGPU][llvm-mc] Support of Trap Handler registers (TTMP0..11 and TBA/TMA)gi...Artem Tamazov2016-04-131-13/+32
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