| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | AMDGPU: Start adding offset fields to flat instructions | Matt Arsenault | 2017-06-12 | 1 | -20/+46 | |
| * | AMDGPU: Remove tfe bit from flat instruction definitions | Matt Arsenault | 2017-05-11 | 1 | -16/+18 | |
| * | [AMDGPU] Get address space mapping by target triple environment | Yaxun Liu | 2017-03-27 | 1 | -6/+6 | |
| * | AMDGPU: split ret/noret patterns for global atomics | Jan Vesely | 2016-12-23 | 1 | -2/+2 | |
| * | AMDGPU: Rename flat operands to match mubuf | Matt Arsenault | 2016-11-29 | 1 | -13/+13 | |
| * | AMDGPU: Add VI i16 support | Tom Stellard | 2016-11-10 | 1 | -0/+6 | |
| * | Revert "AMDGPU: Add VI i16 support" | Tom Stellard | 2016-11-04 | 1 | -6/+0 | |
| * | AMDGPU: Add VI i16 support | Tom Stellard | 2016-11-03 | 1 | -0/+6 | |
| * | AMDGPU: Rename glc operand type | Matt Arsenault | 2016-10-28 | 1 | -2/+2 | |
| * | [AMDGPU] Refactor FLAT TD instructions | Valery Pykhtin | 2016-09-05 | 1 | -0/+524 | |
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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