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* AMDGPU: Remove leftover td fileMatt Arsenault2017-07-221-15/+0
| | | | | | | All of the instructions were moved out of this a while ago, so it's just a useless comment now. llvm-svn: 308815
* [AMDGPU] Refactor VOP1 and VOP2 instruction TD definitionsValery Pykhtin2016-09-231-33/+1
| | | | | | Differential revision: https://reviews.llvm.org/D24738 llvm-svn: 282234
* [AMDGPU] Refactor VOP3 instruction TD definitionsValery Pykhtin2016-09-201-25/+0
| | | | | | Differential revision: https://reviews.llvm.org/D24664 llvm-svn: 281965
* [AMDGPU] Refactor MUBUF/MTBUF instructionsValery Pykhtin2016-09-101-12/+0
| | | | | | Differential revision: https://reviews.llvm.org/D24295 llvm-svn: 281137
* AMDGPU : Fix mqsad_u32_u8 instruction incorrect data type.Wei Ding2016-09-091-1/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D23700 llvm-svn: 281081
* [AMDGPU] Refactor FLAT TD instructionsValery Pykhtin2016-09-051-240/+0
| | | | | | Differential revision: https://reviews.llvm.org/D24072 llvm-svn: 280655
* [AMDGPU] Scalar Memory instructions TD refactoringValery Pykhtin2016-09-011-8/+0
| | | | | | Differential revision: https://reviews.llvm.org/D23996 llvm-svn: 280349
* AMDGPU : Fix QSAD and MQSAD instructions' incorrect data type.Wei Ding2016-08-181-1/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D23689 llvm-svn: 279126
* AMDGPU : Add LLVM intrinsics for SAD related instructions.Wei Ding2016-08-111-6/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D23133 llvm-svn: 278354
* [AMDGPU] refactor DS instruction definitions. NFC.Valery Pykhtin2016-08-011-17/+0
| | | | | | Differential revision: https://reviews.llvm.org/D22522 llvm-svn: 277344
* AMDGPU: Fix flat atomicsMatt Arsenault2016-06-091-33/+38
| | | | | | | | The flat atomics could already be selected, but only when using flat instructions for global memory. Add patterns for flat addresses. llvm-svn: 272345
* AMDGPU: Add fract intrinsicMatt Arsenault2016-05-281-19/+0
| | | | | | | | | Remove broken patterns matching it. This was matching the unsafe math pattern and expanding the fix for the buggy instruction from the pattern. The problems are also on CI. Remove the workarounds and only use fract with unsafe math or from the intrinsic. llvm-svn: 271078
* AMDGPU: Implement i64 global atomicsMatt Arsenault2016-04-121-0/+10
| | | | llvm-svn: 266075
* AMDGPU: Add atomic_inc + atomic_dec intrinsicsMatt Arsenault2016-04-121-1/+5
| | | | | | | These are different than atomicrmw add 1 because they have an additional input value to clamp the result. llvm-svn: 266074
* AMDGPU/SI: Implement atomic load/store for i32 and i64Jan Vesely2016-04-071-0/+18
| | | | | | | | | | Standard load/store instructions with GLC bit set. Reviewers: tstellardAMD, arsenm Differential Revision: http://reviews.llvm.org/D18760 llvm-svn: 265709
* AMDGPU: Implement {BUFFER,FLAT}_ATOMIC_CMPSWAP{,_X2}Tom Stellard2016-04-011-2/+6
| | | | | | | | | | | | | | | | | Summary: Implement BUFFER_ATOMIC_CMPSWAP{,_X2} instructions on all GCN targets, and FLAT_ATOMIC_CMPSWAP{,_X2} on CI+. 32-bit instruction variants tested manually on Kabini and Bonaire. Tests and parts of code provided by Jan Veselý. Patch by: Vedran Miletić Reviewers: arsenm, tstellarAMD, nhaehnle Subscribers: jvesely, scchan, kanarayan, arsenm Differential Revision: http://reviews.llvm.org/D17280 llvm-svn: 265170
* [AMDGPU] Disassembler: Added basic disassembler for AMDGPU targetTom Stellard2016-02-181-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes: - Added disassembler project - Fixed all decoding conflicts in .td files - Added DecoderMethod=“NONE” option to Target.td that allows to disable decoder generation for an instruction. - Created decoding functions for VS_32 and VReg_32 register classes. - Added stubs for decoding all register classes. - Added several tests for disassembler Disassembler only supports: - VI subtarget - VOP1 instruction encoding - 32-bit register operands and inline constants [Valery] One of the point that requires to pay attention to is how decoder conflicts were resolved: - Groups of target instructions were separated by using different DecoderNamespace (SICI, VI, CI) using similar to AssemblerPredicate approach. - There were conflicts in IMAGE_<> instructions caused by two different reasons: 1. dmask wasn’t specified for the output (fixed) 2. There are image instructions that differ only by the number of the address components but have the same encoding by the HW spec. The actual number of address components is determined by the HW at runtime using image resource descriptor starting from the VGPR encoded in an IMAGE instruction. This means that we should choose only one instruction from conflicting group to be the rule for decoder. I didn’t find the way to disable decoder generation for an arbitrary instruction and therefore made a onelinear fix to tablegen generator that would suppress decoder generation when DecoderMethod is set to “NONE”. This is a change that should be reviewed and submitted first. Otherwise I would need to specify different DecoderNamespace for every instruction in the conflicting group. I haven’t checked yet if DecoderMethod=“NONE” is not used in other targets. 3. IMAGE_GATHER decoder generation is for now disabled and to be done later. [/Valery] Patch By: Sam Kolton Differential Revision: http://reviews.llvm.org/D16723 llvm-svn: 261185
* [AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD ↵Tom Stellard2016-02-121-1/+1
| | | | | | | | | | | | | | assembler Historically, AMD internal sp3 assembler has flat_store* addr, data format. To match existing code and to enable reuse, change LLVM definitions to match. Also update MC and CodeGen tests. Differential Revision: http://reviews.llvm.org/D16927 Patch by: Nikolay Haustov llvm-svn: 260694
* AMDGPU: Tidy minor td file issuesMatt Arsenault2016-01-261-10/+2
| | | | | | | | | | Make comments and indentation more consistent. Rearrange a few things to be in a more consistent order, such as organizing subtarget features from those describing an actual device property, and those used as options. llvm-svn: 258789
* AMDGPU/SI: Consolidate FLAT patternsTom Stellard2016-01-051-55/+15
| | | | | | | | | | | | | | | | | | | | | | | Summary: We had to sets of identical FLAT patterns one inside the HasFlatAddressSpace predicate and one inside the useFlatForGloabl predicate. This patch merges these sets into a single pattern under the isCIVI predicate. The reason we can remove the predicates is that when MUBUF instructions are legal, the instruction selector will prefer selecting those over FLAT instructions because MUBUF patterns have a higher complexity score. So, in this case having patterns for FLAT instructions will have no effect. This change also simplifies the process for forcing global address space loads to use FLAT instructions, since we no only have to disable the MUBUF patterns instead of having to disable the MUBUF patterns and enable the FLAT patterns. Reviewers: arsenm, cfang Subscribers: llvm-commits llvm-svn: 256807
* AMDGPU/SI: Move VI SMEM pattern back into VIInstructions.tdTom Stellard2016-01-041-6/+0
| | | | | | | | | | | | Summary: This was accidently moved to CIInstructions.td in r256282 Reviewers: cfang, arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15763 llvm-svn: 256775
* AMDGPU/SI: Fix encoding of flat instructions on VITom Stellard2015-12-241-56/+141
| | | | | | | | | | Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15735 llvm-svn: 256360
* AMDGPU/SI: Remove non-existent flat instructionsTom Stellard2015-12-241-2/+0
| | | | | | | | | | Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15734 llvm-svn: 256357
* AMDGPU/SI: Use flat for global load/store when targeting HSAChangpeng Fang2015-12-221-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: For some reason doing executing an MUBUF instruction with the addr64 bit set and a zero base pointer in the resource descriptor causes the memory operation to be dropped when the shader is executed using the HSA runtime. This kind of MUBUF instruction is commonly used when the pointer is stored in VGPRs. The base pointer field in the resource descriptor is set to zero and and the pointer is stored in the vaddr field. This patch resolves the issue by only using flat instructions for global memory operations when targeting HSA. This is an overly conservative fix as all other configurations of MUBUF instructions appear to work. NOTE: re-commit by fixing a failure in Codegen/AMDGPU/llvm.dbg.value.ll Reviewers: tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15543 llvm-svn: 256282
* Revert "AMDGPU/SI: Use flat for global load/store when targeting HSA"Rafael Espindola2015-12-221-60/+0
| | | | | | | | This reverts commit r256273. It broke CodeGen/AMDGPU/llvm.dbg.value.ll llvm-svn: 256275
* AMDGPU/SI: Use flat for global load/store when targeting HSAChangpeng Fang2015-12-221-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: For some reason doing executing an MUBUF instruction with the addr64 bit set and a zero base pointer in the resource descriptor causes the memory operation to be dropped when the shader is executed using the HSA runtime. This kind of MUBUF instruction is commonly used when the pointer is stored in VGPRs. The base pointer field in the resource descriptor is set to zero and and the pointer is stored in the vaddr field. This patch resolves the issue by only using flat instructions for global memory operations when targeting HSA. This is an overly conservative fix as all other configurations of MUBUF instructions appear to work. Reviewers: tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15543 llvm-svn: 256273
* AMDGPU: Add s_dcache_* instructionsMatt Arsenault2015-09-241-2/+7
| | | | llvm-svn: 248533
* AMDGPU: Add cache invalidation instructions.Matt Arsenault2015-09-241-0/+8
| | | | | | | | | | These are necessary for implementing mem_fence for OpenCL 2.0. The VI assembler tests are disabled since it seems to be using the wrong encoding or opcode. llvm-svn: 248532
* AMDGPU: Improve accuracy of instruction rates for some FP instructionsMatt Arsenault2015-08-221-0/+5
| | | | llvm-svn: 245774
* AMDGPU: Move CI instructions into CIInstructions.tdMatt Arsenault2015-08-221-0/+69
| | | | | | There are still a couple of CI patterns left in SIInstructions. llvm-svn: 245767
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+149
llvm-svn: 239657
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