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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-09-24 19:52:21 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-09-24 19:52:21 +0000 |
| commit | d6adfb401c5e9f7ec111866491ab3223d002a657 (patch) | |
| tree | 83c1afca31b791869f6e155ff30fac5361bba0e7 /llvm/lib/Target/AMDGPU/CIInstructions.td | |
| parent | c116767fecbaaea524ece01fe7cf59808db82c10 (diff) | |
| download | bcm5719-llvm-d6adfb401c5e9f7ec111866491ab3223d002a657.tar.gz bcm5719-llvm-d6adfb401c5e9f7ec111866491ab3223d002a657.zip | |
AMDGPU: Add cache invalidation instructions.
These are necessary for implementing mem_fence for
OpenCL 2.0.
The VI assembler tests are disabled since it seems to be
using the wrong encoding or opcode.
llvm-svn: 248532
Diffstat (limited to 'llvm/lib/Target/AMDGPU/CIInstructions.td')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/CIInstructions.td | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/CIInstructions.td b/llvm/lib/Target/AMDGPU/CIInstructions.td index 9ec6fd12499..2bb740beebb 100644 --- a/llvm/lib/Target/AMDGPU/CIInstructions.td +++ b/llvm/lib/Target/AMDGPU/CIInstructions.td @@ -100,6 +100,14 @@ defm DS_WRAP_RTN_F32 : DS_1A1D_RET <0x34, "ds_wrap_rtn_f32", VGPR_32, "ds_wrap_f // DS_CONDXCHG32_RTN_B128 //===----------------------------------------------------------------------===// +// MUBUF Instructions +//===----------------------------------------------------------------------===// + +defm BUFFER_WBINVL1_VOL : MUBUF_Invalidate <mubuf<0x70, 0x3f>, + "buffer_wbinvl1_vol", int_amdgcn_buffer_wbinvl1_vol +>; + +//===----------------------------------------------------------------------===// // Flat Instructions //===----------------------------------------------------------------------===// |
