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path: root/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
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* Fixed/Recommitted r267733 "[AMDGPU][llvm-mc] Add support of TTMP quads. Rewor...Artem Tamazov2016-04-291-1/+2
* AMDGPU/SI: Assembler: Unify parsing/printing of operands.Nikolay Haustov2016-04-291-238/+224
* Revert "[AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for ...Chad Rosier2016-04-271-2/+1
* Silence a -Wdangling-elseReid Kleckner2016-04-271-1/+2
* [AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for SMRD.Artem Tamazov2016-04-271-1/+2
* [AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware regis...Artem Tamazov2016-04-271-9/+28
* [AMDGPU] Assembler: basic support for SDWA instructionsSam Kolton2016-04-261-0/+112
* [AMDGPU][llvm-mc] s_getreg/setreg* - Add hwreg(...) syntax.Artem Tamazov2016-04-251-0/+94
* [AMDGPU] Assembler: prevent parseDPPCtrlOps from eating invalid tokensSam Kolton2016-04-211-2/+14
* AMDGPU/SI: Assembler: improvements to support trap handlers.Nikolay Haustov2016-04-201-69/+123
* [NFC] Header cleanupMehdi Amini2016-04-181-1/+0
* [AMDGPU][llvm-mc] Support of Trap Handler registers (TTMP0..11 and TBA/TMA)gi...Artem Tamazov2016-04-131-21/+34
* [AMDGPU] Assembler: Change dpp_ctrl syntax to match sp3Sam Kolton2016-03-181-46/+88
* [AMDGPU] AsmParser: Factor out parseRegister. NFC.Valery Pykhtin2016-03-141-24/+40
* [AMDGPU] AsmParser: refactor post push_back vector access. NFC.Valery Pykhtin2016-03-141-6/+5
* [AMDGPU] AsmParser: remove redundant isReg checks. NFC.Valery Pykhtin2016-03-141-7/+7
* [AMDGPU] Assembler: Support DPP instructions.Sam Kolton2016-03-091-5/+175
* [AMDGPU] Assembler: Support abs() syntax.Nikolay Haustov2016-03-091-2/+19
* [AMDGPU] Using table-driven amd_kernel_code_t field parser in assembler.Valery Pykhtin2016-03-061-157/+6
* Test commit accessSam Kolton2016-03-041-1/+1
* AMDGPU/SI: add llvm.amdgcn.image.atomic.* intrinsicsNikolay Haustov2016-03-041-3/+47
* Revert "[AMDGPU] Using table-driven amd_kernel_code_t field parser in assembl...Nikolay Haustov2016-03-021-6/+157
* [AMDGPU] Using table-driven amd_kernel_code_t field parser in assembler.Nikolay Haustov2016-03-021-157/+6
* [TableGen] AsmMatcher: Skip optional operands in the midle of instruction if ...Nikolay Haustov2016-03-011-18/+11
* [AMDGPU] Assembler: Basic support for MIMGNikolay Haustov2016-02-261-6/+70
* [AMDGPU] Assembler: Simplify handling of optional operandsNikolay Haustov2016-02-251-72/+59
* Revert r261742, "[AMDGPU] Assembler: Simplify handling of optional operands"NAKAMURA Takumi2016-02-251-61/+72
* [AMDGPU] Assembler: Simplify handling of optional operandsNikolay Haustov2016-02-241-72/+61
* [AMDGPU][llvm-mc] Support for 32-bit inline literalsTom Stellard2016-02-221-33/+58
* Test commit access.Nikolay Haustov2016-02-181-1/+0
* Fix uninitialized memory read.Benjamin Kramer2016-02-121-2/+2
* [AMDGPU] Fix for "v_div_scale_f64 reg, vcc, ..." parsingTom Stellard2016-02-111-2/+2
* [AMDGPU] Assembler: Fix VOP3 only instructionsTom Stellard2016-02-111-53/+92
* AMDGPU: waitcnt operand fixesTom Stellard2016-01-281-3/+3
* Move MCTargetAsmParser.h to llvm/MC/MCParser where it belongs.Benjamin Kramer2016-01-271-5/+5
* AMDGPU/SI: Fix encoding for FLAT_SCRATCH registers on VITom Stellard2015-12-211-5/+8
* AMDGPU/SI: Emit constant arrays in the .hsrodata_readonly_agent sectionTom Stellard2015-12-031-0/+10
* AMDGPU/SI: Correctly emit agent global segment variables when targeting HSATom Stellard2015-12-021-0/+50
* AMDGPU: Disallow flat_scr in SI assemblerMatt Arsenault2015-12-011-3/+24
* Reduce the size of MCRelaxableFragment.Akira Hatanaka2015-11-141-2/+4
* [MCTargetAsmParser] Move the member varialbes that referenceAkira Hatanaka2015-11-141-9/+7
* AMDGPU/SI: Emit HSA kernels with symbol type STT_AMDGPU_HSA_KERNELTom Stellard2015-11-061-0/+18
* AMDGPU: Disallow s[102:103] on VI in assemblerMatt Arsenault2015-11-051-2/+28
* AMDGPU: Make flat_scratch name consistentMatt Arsenault2015-11-031-3/+3
* AMDGPU: Fix asserts on invalid register rangesMatt Arsenault2015-11-031-5/+13
* AMDGPU: Fix off by one error in register parsingMatt Arsenault2015-11-031-4/+5
* AMDGPU: Print modifiers when dumping AMDGPUOperandMatt Arsenault2015-10-241-1/+1
* AMDGPU: Fix parsing of 32-bit literals with sign bit setMatt Arsenault2015-10-231-3/+1
* AMDGPU/SI: Add 64-bit versions of v_nop and v_clrexcpTom Stellard2015-10-061-2/+19
* AMDGPU/SI: Use .hsatext section instead of .text for HSATom Stellard2015-09-251-0/+10
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