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path: root/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
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* AMDGPU: Adding more median3 patternsAakanksha Patil2018-11-121-6/+18
* DAG: Change behavior of fminnum/fmaxnum nodesMatt Arsenault2018-10-221-0/+28
* AMDGPU: Remove remnants of old address space mappingMatt Arsenault2018-08-311-18/+18
* [AMDGPU] Support idot2 pattern.Farhana Aleen2018-08-211-0/+3
* AMDGPU: Reduce code size with fcanonicalize (fneg x)Matt Arsenault2018-07-301-0/+1
* AMDGPU/R600: Add MOV instructions to BFE patternsJan Vesely2018-07-271-5/+5
* AMDGPU: Separate R600 and GCN TableGen filesTom Stellard2018-06-281-16/+72
* AMDGPU: Add patterns for i32/i64 local atomic load/storeMatt Arsenault2018-06-221-0/+3
* [AMDGPU] Recognize x & ~(-1 << y) pattern.Roman Lebedev2018-06-151-0/+6
* [AMDGPU] Recognize x & ((1 << y) - 1) pattern.Roman Lebedev2018-06-151-0/+7
* [AMDGPU] Recognize x & (-1 >> (32 - y)) pattern.Roman Lebedev2018-06-151-0/+7
* [AMDGPU] Supported ds_write_b128 generation.Farhana Aleen2018-03-161-0/+3
* [AMDGPU] Supported ds_read_b128 generation; Widened vector length for local a...Farhana Aleen2018-03-091-0/+8
* AMDGPU: Select BFI patterns with 64-bit intsMatt Arsenault2018-02-071-4/+43
* AMDGPU: Move ADDRIndirect complex pattern into R600Instructions.tdTom Stellard2018-01-291-1/+0
* AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instructionJan Vesely2017-12-041-0/+1
* AMDGPU: Select d16 loads into low component of registerMatt Arsenault2017-11-131-0/+23
* AMDGPU: Add new intrinsic llvm.amdgcn.kill(i1)Marek Olsak2017-10-241-1/+0
* AMDGPU: Cleanup local atomic node namesMatt Arsenault2017-10-231-16/+4
* AMDGPU: Remove global isGCN predicatesMatt Arsenault2017-10-031-23/+27
* AMDGPU: Move r600 only code into r600 only td fileMatt Arsenault2017-09-201-53/+0
* AMDGPU: Match load d16 hi instructionsMatt Arsenault2017-09-201-1/+6
* AMDGPU: Cleanup load/store PatFragsMatt Arsenault2017-09-201-120/+97
* AMDGPU: Match store d16_hi instructionsMatt Arsenault2017-09-201-18/+45
* [AMDGPU] Use v_max_f* for fcanonicalizeStanislav Mekhanoshin2017-08-301-3/+6
* [AMDGPU][MC][GFX9] Added integer clamping support for VOP3 opcodesDmitry Preobrazhensky2017-08-161-4/+6
* AMDGPU: Start selecting global instructionsMatt Arsenault2017-07-291-0/+1
* [AMDGPU][MC] Added check for truncation of SOPK imm operandDmitry Preobrazhensky2017-04-261-0/+16
* [AMDGPU] Get address space mapping by target triple environmentYaxun Liu2017-03-271-16/+16
* AMDGPU: Use v_med3_{f16|i16|u16}Matt Arsenault2017-02-271-3/+4
* AMDGPU: Support v2i16/v2f16 packed operationsMatt Arsenault2017-02-271-0/+10
* AMDGPU: Add another BFE patternMatt Arsenault2017-02-231-36/+50
* AMDGPU: Redefine clamp node as clamp 0.0-1.0Matt Arsenault2017-02-211-1/+1
* AMDGPU: Use source modifiers with f16->f32 conversionsMatt Arsenault2017-02-021-0/+3
* AMDGPU: Generalize matching of v_med3_f32Matt Arsenault2017-01-311-0/+2
* [AMDGPU] Implement f16 fcopysign and fcopysign(f32, f64)Konstantin Zhuravlyov2017-01-131-0/+6
* AMDGPU: Fix sub_oneuse being marked commutativeMatt Arsenault2017-01-121-1/+2
* AMDGPU: split ret/noret patterns for global atomicsJan Vesely2016-12-231-18/+48
* AMDGPU: Implement f16 fcanonicalizeMatt Arsenault2016-12-221-0/+1
* [AMDGPU] Add f16 support (VI+)Konstantin Zhuravlyov2016-11-131-0/+1
* AMDGPU: Add VI i16 supportTom Stellard2016-11-101-3/+3
* Revert "AMDGPU: Add VI i16 support"Tom Stellard2016-11-041-3/+3
* AMDGPU: Add VI i16 supportTom Stellard2016-11-031-3/+3
* [AMDGPU] add fcopysign(f64, f32) patternValery Pykhtin2016-10-201-0/+9
* Target: Remove unused patterns and transforms. NFC.Peter Collingbourne2016-10-071-13/+0
* AMDGPU] Assembler: better support for immediate literals in assembler.Sam Kolton2016-09-091-7/+0
* [AMDGPU] Refactor FLAT TD instructionsValery Pykhtin2016-09-051-19/+0
* AMDGPU : Add V_SAD_U32 instruction pattern.Wei Ding2016-08-241-0/+8
* AMDGPU: Fix i1 fp_to_intMatt Arsenault2016-07-221-1/+2
* AMDGPU/R600: Remove intrinsics with no tests and no usersMatt Arsenault2016-07-141-4/+4
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