summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
Commit message (Expand)AuthorAgeFilesLines
* AMDGPU/GlobalISel: Fix import of integer med3Matt Arsenault2020-01-091-24/+0
* AMDGPU: Eliminate more legacy codepred address space PatFragsMatt Arsenault2020-01-091-84/+0
* AMDGPU: Use new PatFrag system for d16 storesMatt Arsenault2020-01-091-13/+7
* AMDGPU: Annotate EXTRACT_SUBREGs with source register classesMatt Arsenault2020-01-071-24/+24
* AMDGPU: Use ImmLeafMatt Arsenault2020-01-071-2/+2
* AMDGPU/GlobalISel: Select scalar v2s16 G_BUILD_VECTORMatt Arsenault2020-01-061-6/+16
* AMDGPU: Refactor treatment of denormal modeMatt Arsenault2019-11-191-6/+9
* [AMDGPU] deduplicate tablegen predicatesStanislav Mekhanoshin2019-11-041-6/+14
* AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHGMatt Arsenault2019-10-251-14/+1
* AMDGPU/GlobalISel: Select local atomic cmpxchgMatt Arsenault2019-08-011-16/+12
* AMDGPU: Start redefining atomic PatFragsMatt Arsenault2019-08-011-38/+32
* AMDGPU/GlobalISel: Select simple local storesMatt Arsenault2019-08-011-1/+3
* AMDGPU/GlobalISel: Select local loadsMatt Arsenault2019-08-011-0/+2
* TableGen: Add MinAlignment predicateMatt Arsenault2019-07-311-19/+21
* AMDGPU: Avoid emitting "true" predicatesMatt Arsenault2019-07-301-1/+1
* AMDGPU: Redefine setcc condition PatLeafsMatt Arsenault2019-07-191-55/+23
* AMDGPU: Replace store PatFragsMatt Arsenault2019-07-161-12/+32
* AMDGPU: Redefine load PatFragsMatt Arsenault2019-07-161-70/+97
* AMDGPU: Avoid code predicates for extload PatFragsMatt Arsenault2019-07-161-29/+16
* [AMDGPU] gfx908 atomic fadd and atomic pk_faddStanislav Mekhanoshin2019-07-111-4/+6
* AMDGPU: Split extload/zextload local load patternsMatt Arsenault2019-07-081-2/+4
* AMDGPU: Support GDS atomicsNicolai Haehnle2019-07-011-0/+21
* [AMDGPU] gfx1010 base changes for wave32Stanislav Mekhanoshin2019-06-131-1/+3
* [AMDGPU] Remove now unused V2FP16_ONE constant def. NFC.Stanislav Mekhanoshin2019-05-131-1/+0
* AMDGPU: Move d16 load matching to preprocess stepMatt Arsenault2019-03-081-3/+3
* AMDGPU: Remove GCN features and predicatesMatt Arsenault2019-02-081-11/+3
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* AMDGPU: Raise the priority of MAD24 in instruction selection.Changpeng Fang2019-01-151-0/+2
* [AMDGPU] Add and update scalar instructionsGraham Sellers2018-11-291-0/+8
* AMDGPU: Adding more median3 patternsAakanksha Patil2018-11-121-6/+18
* DAG: Change behavior of fminnum/fmaxnum nodesMatt Arsenault2018-10-221-0/+28
* AMDGPU: Remove remnants of old address space mappingMatt Arsenault2018-08-311-18/+18
* [AMDGPU] Support idot2 pattern.Farhana Aleen2018-08-211-0/+3
* AMDGPU: Reduce code size with fcanonicalize (fneg x)Matt Arsenault2018-07-301-0/+1
* AMDGPU/R600: Add MOV instructions to BFE patternsJan Vesely2018-07-271-5/+5
* AMDGPU: Separate R600 and GCN TableGen filesTom Stellard2018-06-281-16/+72
* AMDGPU: Add patterns for i32/i64 local atomic load/storeMatt Arsenault2018-06-221-0/+3
* [AMDGPU] Recognize x & ~(-1 << y) pattern.Roman Lebedev2018-06-151-0/+6
* [AMDGPU] Recognize x & ((1 << y) - 1) pattern.Roman Lebedev2018-06-151-0/+7
* [AMDGPU] Recognize x & (-1 >> (32 - y)) pattern.Roman Lebedev2018-06-151-0/+7
* [AMDGPU] Supported ds_write_b128 generation.Farhana Aleen2018-03-161-0/+3
* [AMDGPU] Supported ds_read_b128 generation; Widened vector length for local a...Farhana Aleen2018-03-091-0/+8
* AMDGPU: Select BFI patterns with 64-bit intsMatt Arsenault2018-02-071-4/+43
* AMDGPU: Move ADDRIndirect complex pattern into R600Instructions.tdTom Stellard2018-01-291-1/+0
* AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instructionJan Vesely2017-12-041-0/+1
* AMDGPU: Select d16 loads into low component of registerMatt Arsenault2017-11-131-0/+23
* AMDGPU: Add new intrinsic llvm.amdgcn.kill(i1)Marek Olsak2017-10-241-1/+0
* AMDGPU: Cleanup local atomic node namesMatt Arsenault2017-10-231-16/+4
* AMDGPU: Remove global isGCN predicatesMatt Arsenault2017-10-031-23/+27
* AMDGPU: Move r600 only code into r600 only td fileMatt Arsenault2017-09-201-53/+0
OpenPOWER on IntegriCloud