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path: root/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
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* AMDGPU: Improve llvm.round.f64 lowering for CI+Matt Arsenault2019-12-301-1/+1
* AMDGPU: Select global atomicrmw faddMatt Arsenault2019-11-061-1/+0
* AMDGPU: Select basic interp directly from intrinsicsMatt Arsenault2019-10-211-3/+0
* AMDGPU: Move SelectFlatOffset back into AMDGPUISelDAGToDAGMatt Arsenault2019-10-111-4/+0
* AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUEMatt Arsenault2019-09-091-0/+1
* AMDGPU: Remove pointless wrapper nodes for init.exec intrinsicsMatt Arsenault2019-09-091-2/+0
* AMDGPU: Remove unused custom node definitionMatt Arsenault2019-09-011-2/+0
* AMDGPU: Combine directly on mul24 intrinsicsMatt Arsenault2019-08-271-0/+1
* Re-commit: [AMDGPU] Use S_DENORM_MODE for gfx10Austin Kerbow2019-08-061-0/+3
* Revert "[AMDGPU] Use S_DENORM_MODE for gfx10"Dmitri Gribenko2019-08-051-3/+0
* [AMDGPU] Use S_DENORM_MODE for gfx10Austin Kerbow2019-08-051-0/+3
* AMDGPU: add missing llvm.amdgcn.{raw,struct}.buffer.atomic.{inc,dec}Nicolai Haehnle2019-08-051-0/+2
* [AMDGPU] gfx908 atomic fadd and atomic pk_faddStanislav Mekhanoshin2019-07-111-0/+4
* [X86][AMDGPU][DAGCombiner] Move call to allowsMemoryAccess into isLoadBitCast...Craig Topper2019-07-091-1/+2
* AMDGPU: Write LDS objects out as global symbols in code generationNicolai Haehnle2019-06-251-0/+1
* [SelectionDAG][x86] limit post-legalization store merging by typeSanjay Patel2019-06-041-1/+1
* [AMDGPU] gfx1010 VMEM and SMEM implementationStanislav Mekhanoshin2019-04-301-0/+4
* [AMDGPU] Implemented dwordx3 variants of buffer/tbuffer load/store intrinsicsTim Renouf2019-03-221-1/+0
* [AMDGPU] Support for v3i32/v3f32Tim Renouf2019-03-211-0/+14
* [AMDGPU] Add buffer/load 8/16 bit overloaded intrinsicsRyan Taylor2019-03-191-0/+6
* [TargetLowering] Add code size information on isFPImmLegal. NFCAdhemerval Zanella2019-03-181-1/+2
* AMDGPU: Move d16 load matching to preprocess stepMatt Arsenault2019-03-081-0/+7
* Adjust documentation for git migration.James Y Knight2019-01-291-8/+8
* [AMDGPU] Add intrinsics for 16 bit interpolationTim Corringham2019-01-281-0/+3
* Codegen support for atomicrmw fadd/fsubMatt Arsenault2019-01-221-1/+0
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* AMDGPU: Add llvm.amdgcn.ds.ordered.add & swapMarek Olsak2019-01-161-0/+1
* DAG: Change behavior of fminnum/fmaxnum nodesMatt Arsenault2018-10-221-0/+1
* AMDGPU: Expand atomicrmw nand in IRMatt Arsenault2018-10-021-0/+2
* AMDGPU: Remove remnants of old address space mappingMatt Arsenault2018-08-311-6/+0
* [AMDGPU] Add support for multi-dword s.buffer.load intrinsicTim Renouf2018-08-251-0/+1
* AMDGPU: Fix not respecting byval alignment in call frame setupMatt Arsenault2018-08-221-1/+0
* AMDGPU: Custom lower fexpMatt Arsenault2018-08-161-1/+2
* AMDGPU: Address todo for handling 1/(2 pi)Matt Arsenault2018-08-151-0/+2
* DAG: Enhance isKnownNeverNaNMatt Arsenault2018-08-031-0/+5
* Reapply "AMDGPU: Fix handling of alignment padding in DAG argument lowering"Matt Arsenault2018-07-201-2/+5
* [AMDGPU] [AMDGPU] Support a fdot2 pattern.Farhana Aleen2018-07-161-0/+1
* Revert "AMDGPU: Fix handling of alignment padding in DAG argument lowering"Evgeniy Stepanov2018-07-141-5/+2
* AMDGPU: Fix handling of alignment padding in DAG argument loweringMatt Arsenault2018-07-131-2/+5
* AMDGPU: Refactor Subtarget classesTom Stellard2018-07-111-3/+3
* AMDGPU: Separate R600 and GCN TableGen filesTom Stellard2018-06-281-3/+4
* AMDGPU: Remove MFI::ABIArgOffsetMatt Arsenault2018-06-281-1/+1
* [AMDGPU] Convert rcp to rcp_iflagStanislav Mekhanoshin2018-06-271-0/+2
* AMDGPU: Remove old-style image intrinsicsNicolai Haehnle2018-06-211-84/+0
* AMDGPU: Move isSDNodeSourceOfDivergence() implementation to SITargetLoweringTom Stellard2018-06-131-2/+0
* [AMDGPU] DAG combine to produce V_PERM_B32Stanislav Mekhanoshin2018-06-121-0/+1
* AMDGPU/R600: Remove code for handling AMDGPUISD::CLAMPTom Stellard2018-05-241-1/+0
* AMDGPU: Move AMDGPUTargetLowering::isFPExtFoldable() into SITargetLoweringTom Stellard2018-05-221-1/+0
* AMDGPU: Custom lower v4i16/v4f16 vector operationsMatt Arsenault2018-05-161-0/+4
* AMDGPU: Add combine for trunc of bitcast from build_vectorMatt Arsenault2018-05-091-0/+1
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