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* [AArch64] Improve orr+movk sequences for MOVi64imm.Eli Friedman2018-05-241-115/+96
* [AArch64] Take advantage of variable shift/rotate amount implicit mod operation.Geoff Berry2018-05-241-0/+111
* [CodeGen][AArch64] Use RegUnits to track register aliases. (NFC)Chad Rosier2018-05-231-40/+27
* [AArch64] Use addAliasForDirective to support data directivesAlex Bradbury2018-05-231-23/+7
* Delete unused variable from r333015.Eli Friedman2018-05-221-3/+0
* [MachineOutliner] Add "thunk" outlining for AArch64.Eli Friedman2018-05-221-18/+83
* [DAGCombine][X86][AArch64] Masked merge unfolding: vector edition.Roman Lebedev2018-05-211-3/+12
* MC: Separate creating a generic object writer from creating a target object w...Peter Collingbourne2018-05-215-39/+25
* MC: Change MCAsmBackend::writeNopData() to take a raw_ostream instead of an M...Peter Collingbourne2018-05-211-10/+9
* Support: Simplify endian stream interface. NFCI.Peter Collingbourne2018-05-181-1/+1
* MC: Change the streamer ctors to take an object writer instead of a stream. N...Peter Collingbourne2018-05-185-19/+23
* [ExynosM3] Fix scheduling info.Clement Courbet2018-05-181-35/+35
* [MachineOutliner] Count savings from outlining in bytes.Eli Friedman2018-05-181-11/+15
* [AArch64][SVE] Asm: Support for structured ST2, ST3 and ST4 (scalar+scalar) s...Sander de Smalen2018-05-172-1/+37
* [MachineOutliner] Don't outline instructions that modify SP.Eli Friedman2018-05-161-0/+8
* [MachineOutliner] Don't save/restore LR for tail calls.Eli Friedman2018-05-161-3/+4
* [AArch64][SVE] Improve diagnostics for vectors with incorrect element-size.Sander de Smalen2018-05-162-11/+42
* [AArch64] Gangup loads and stores for pairing.Sirish Pande2018-05-161-0/+2
* [AArch64][SVE] Asm: Support for gather PRF prefetch instructionsSander de Smalen2018-05-162-0/+159
* [GlobalISel][IRTranslator] Split aggregates during IR translation.Amara Emerson2018-05-161-0/+3
* [AArch64] Support "S" inline assembler constraintPeter Smith2018-05-162-1/+25
* [AArch64][SVE] Asm: Support for structured LD2, LD3 and LD4 (scalar+scalar) l...Sander de Smalen2018-05-162-0/+36
* [AArch64][SVE] Asm: Support for contiguous PRF prefetch instructions.Sander de Smalen2018-05-164-2/+77
* [AArch64] Improve single vector lane unscaled storesEvandro Menezes2018-05-151-0/+16
* [AArch64] Improve single vector lane storesEvandro Menezes2018-05-141-20/+57
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-1419-390/+427
* [AArch64][SVE] Extend parsing of Prefetch operation for SVE.Sander de Smalen2018-05-147-10/+99
* [AArch64] Fix performPostLD1Combine to check for constant lane index.Geoff Berry2018-05-111-1/+10
* [CGP] Split large data structres to sink more GEPsHaicheng Wu2018-05-102-0/+7
* [AArch64] Improve cost of vector division by constantAdhemerval Zanella2018-05-091-0/+22
* Revert r331816 and r331820 - [globalisel] Add a combiner helpers for extendin...Daniel Sanders2018-05-094-113/+0
* [DebugInfo] Examine all uses of isDebugValue() for debug instructions.Shiva Chen2018-05-093-3/+3
* [globalisel] Add a combiner helpers for extending loads and use them in a pre...Daniel Sanders2018-05-084-0/+113
* [AArch64][SVE] Asm: Support for LD1R load-and-replicate scalar instructions.Sander de Smalen2018-05-084-1/+93
* [AArch64] Disallow vector operand if FPR128 Q register is required.Sander de Smalen2018-05-083-206/+225
* [globalisel] Update GlobalISel emitter to match new representation of extendi...Daniel Sanders2018-05-052-4/+37
* Fix a bunch of places where operator-> was used directly on the return from d...Craig Topper2018-05-051-2/+1
* Fast Math Flag mapping into SDNodeMichael Berg2018-05-041-2/+2
* [AArch64] Custom Lower MULLH{S,U} for v16i8, v8i16, and v4i32Adhemerval Zanella2018-05-042-2/+89
* [COFF, ARM64] Hook up a few remaining relocationsMartin Storsjo2018-05-021-0/+9
* [AArch64][SVE] Asm: Support for LDR/STR fill and spill instructions.Sander de Smalen2018-05-022-1/+109
* [AArch64][SVE] Asm: Support for scatter ST1 store instructions.Sander de Smalen2018-05-022-0/+172
* [AArch64][SVE] Asm: Support for non-temporal, contiguous LDNT1/STNT1 load/sto...Sander de Smalen2018-05-022-0/+150
* [AArch64][SVE] Asm: Support for LD1RQ load-and-replicate quad-word vector ins...Sander de Smalen2018-05-024-0/+77
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-0114-71/+71
* [AArch64][SVE] Asm: Support for contiguous ST1 (scalar+scalar) store instruct...Sander de Smalen2018-05-012-1/+43
* Fix infinite loop after r331115Daniel Sanders2018-04-301-1/+2
* [AArch64][SVE] Asm: Improve diagnostics for gather loads.Sander de Smalen2018-04-303-19/+38
* [AArch64][AsmParser] NFC: Cleanup of addOperands functionsSander de Smalen2018-04-294-230/+81
* [AArch64][SVE] Asm: Support for gather LD1/LDFF1 (vector + imm) load instruct...Sander de Smalen2018-04-294-4/+156
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