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* Change the last few internal StringRef triples into Triple objects.Daniel Sanders2015-07-061-1/+1
| | | | | | | | | | | | | | | | | | | | Summary: This concludes the patch series to eliminate StringRef forms of GNU triples from the internals of LLVM that began in r239036. At this point, the StringRef-form of GNU Triples should only be used in the public API (including IR serialization) and a couple objects that directly interact with the API (most notably the Module class). The next step is to replace these Triple objects with the TargetTuple object that will represent our authoratative/unambiguous internal equivalent to GNU Triples. Reviewers: rengolin Subscribers: llvm-commits, jholewinski, ted, rengolin Differential Revision: http://reviews.llvm.org/D10962 llvm-svn: 241472
* [AArch64] Add v8.1a atomic instructionsVladimir Sukharev2015-06-021-0/+40
| | | | | | | | | | | | Patch by: Tom Coxon Reviewers: t.p.northover Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8501 llvm-svn: 238818
* MC: Modernize MCOperand API naming. NFC.Jim Grosbach2015-05-131-49/+49
| | | | | | MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
* [AArch64] Add v8.1a "Limited Ordering Regions" extensionVladimir Sukharev2015-04-161-0/+8
| | | | | | | | | | | | Reviewers: t.p.northover Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8499 Patch by: Tom Coxon llvm-svn: 235105
* [AArch64] Refactor AArch64NamedImmMapper to become dependent on subtarget ↵Vladimir Sukharev2015-04-161-1/+4
| | | | | | | | | | | | | | | | | | | | | | features. In order to introduce v8.1a-specific entities, Mappers should be aware of SubtargetFeatures available. This patch introduces refactoring, that will then allow to easily introduce: - v8.1-specific "pan" PState for PStateMapper (PAN extension) - v8.1-specific sysregs for SysRegMapper (LOR,VHE extensions) Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8496 Patch by Tom Coxon llvm-svn: 235089
* unique_ptrify the RelInfo parameter to TargetRegistry::createMCSymbolizerDavid Blaikie2015-01-181-7/+5
| | | | llvm-svn: 226416
* Pass an ArrayRef to MCDisassembler::getInstruction.Rafael Espindola2014-11-121-5/+2
| | | | | | | | | | | | With this patch MCDisassembler::getInstruction takes an ArrayRef<uint8_t> instead of a MemoryObject. Even on X86 there is a maximum size an instruction can have. Given that, it seems way simpler and more efficient to just pass an ArrayRef to the disassembler instead of a MemoryObject and have it do a virtual call every time it wants some extra bytes. llvm-svn: 221751
* Misc style fixes. NFC.Rafael Espindola2014-11-101-10/+10
| | | | | | | | | | | | | This fixes a few cases of: * Wrong variable name style. * Lines longer than 80 columns. * Repeated names in comments. * clang-format of the above. This make the next patch a lot easier to read. llvm-svn: 221615
* [AArch64] Allow access to all system registers with MRS/MSR instructions.Tom Coxon2014-10-011-20/+4
| | | | | | | | | | | | | | | | | | | | | The A64 instruction set includes a generic register syntax for accessing implementation-defined system registers. The syntax for these registers is: S<op0>_<op1>_<CRn>_<CRm>_<op2> The encoding space permitted for implementation-defined system registers is: op0 op1 CRn CRm op2 11 xxx 1x11 xxxx xxx The full encoding space can now be accessed: op0 op1 CRn CRm op2 xx xxx xxxx xxxx xxx This is useful to anyone needing to write assembly code supporting new system registers before the assembler has learned the official names for them. llvm-svn: 218753
* [AArch64] Remove unnecessary whitespace. (Test commit)Tom Coxon2014-09-301-2/+2
| | | | llvm-svn: 218680
* Fix left shifts of negative integers in AArch64 InstPrinter/DisassemblerAlexey Samsonov2014-09-021-3/+3
| | | | | | | | | | | | | | | | | | | Summary: Left shift of negative integer is an undefined behavior, and is reported by UBSan. It's ok for imm values to be negative, so we can just replace left shifts with multiplications. Test Plan: check-llvm test suite Reviewers: t.p.northover Reviewed By: t.p.northover Subscribers: aemerson, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D5132 llvm-svn: 216910
* Run sort_includes.py on the AArch64 backend.Benjamin Kramer2014-07-251-2/+2
| | | | | | No functionality change. llvm-svn: 213938
* AArch64: remove "arm64_be" support in favour of "aarch64_be".Tim Northover2014-07-231-6/+2
| | | | | | | | | There really is no arm64_be: it was a useful fiction to test big-endian support while both backends existed in parallel, but now the only platform that uses the name (iOS) doesn't have a big-endian variant, let alone one called "arm64_be". llvm-svn: 213748
* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-241-0/+1559
| | | | | | | | | | | | | | | This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
* AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.Tim Northover2014-05-241-1572/+0
| | | | | | | | | | | | | | | | I'm doing this in two phases for a better "git blame" record. This commit removes the previous AArch64 backend and redirects all functionality to ARM64. It also deduplicates test-lines and removes orphaned AArch64 tests. The next step will be "git mv ARM64 AArch64" and rewire most of the tests. Hopefully LLVM is still functional, though it would be even better if no-one ever had to care because the rename happens straight afterwards. llvm-svn: 209576
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-1/+1
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. AArch64 edition llvm-svn: 207510
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-2/+2
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* [MC] Require an MCContext when constructing an MCDisassembler.Lang Hames2014-04-151-8/+7
| | | | | | | | | | | | | | | | This patch re-introduces the MCContext member that was removed from MCDisassembler in r206063, and requires that an MCContext be passed in at MCDisassembler construction time. (Previously the MCContext member had been initialized in an ad-hoc fashion after construction). The MCCContext member can be used by MCDisassembler sub-classes to construct constant or target-specific MCExprs. This patch updates disassemblers for in-tree targets, and provides the MCRegisterInfo instance that some disassemblers were using through the MCContext (previously those backends were constructing their own MCRegisterInfo instances). llvm-svn: 206241
* Add AArch64 big endian Target (aarch64_be)Christian Pirker2014-02-241-1/+3
| | | | llvm-svn: 202024
* Remove unnecessary include of AArch64GenInstrInfo.inc from ↵Craig Topper2014-02-031-1/+0
| | | | | | AArch64Disassembler.cpp. None of the GET_ defines were set that would make the include do anything. llvm-svn: 200677
* Fix known typosAlp Toker2014-01-241-1/+1
| | | | | | | Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. llvm-svn: 200018
* Re-sort all of the includes with ./utils/sort_includes.py so thatChandler Carruth2014-01-071-4/+4
| | | | | | | | | | subsequent changes are easier to review. About to fix some layering issues, and wanted to separate out the necessary churn. Also comment and sink the include of "Windows.h" in three .inc files to match the usage in Memory.inc. llvm-svn: 198685
* [AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction.Kevin Qin2013-11-291-0/+36
| | | | llvm-svn: 195936
* AArch64: Fix a bug about disassembling post-index load single element to 4 ↵Hao Liu2013-11-281-4/+4
| | | | | | vectors llvm-svn: 195903
* Fixed a bug about disassembling AArch64 post-index load/store single element ↵Hao Liu2013-11-251-9/+14
| | | | | | | | | | instructions. ie. echo "0x00 0x04 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble echo "0x00 0x00 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble will be disassembled into the same instruction st1 {v0b}[0], [x0], x0. llvm-svn: 195591
* Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.Hao Liu2013-11-191-1/+428
| | | | llvm-svn: 195078
* [AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalarChad Rosier2013-11-121-0/+10
| | | | | | | | copy in MC layer. Added the MC layer tests. Fixed triple setting in test cases. Patch by Ana Pazos <apazos@codeaurora.org>. llvm-svn: 194501
* Implement AArch64 post-index vector load/store multiple N-element structure ↵Hao Liu2013-11-051-0/+108
| | | | | | | | | | | | class SIMD(lselem-post). Including following 14 instructions: 4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4). llvm-svn: 194043
* [AArch64] Add support for NEON scalar shift immediate instructions.Chad Rosier2013-10-311-0/+52
| | | | llvm-svn: 193790
* Implement AArch64 vector load/store multiple N-element structure class ↵Hao Liu2013-10-101-0/+72
| | | | | | | | | | | | SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4). llvm-svn: 192361
* Revert "Implement AArch64 vector load/store multiple N-element structure ↵Rafael Espindola2013-10-101-53/+0
| | | | | | | | class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)." This reverts commit r192352. It broke the build. llvm-svn: 192354
* Implement AArch64 vector load/store multiple N-element structure class ↵Hao Liu2013-10-101-0/+53
| | | | | | | | | | | | SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4). llvm-svn: 192352
* Implement aarch64 neon instruction set AdvSIMD (3V elem).Jiangning Liu2013-10-041-0/+12
| | | | llvm-svn: 191944
* AArch64: use RegisterOperand for NEON registers.Tim Northover2013-09-131-30/+2
| | | | | | | | | | | | | | | | Previously we modelled VPR128 and VPR64 as essentially identical register-classes containing V0-V31 (which had Q0-Q31 as "sub_alias" sub-registers). This model is starting to cause significant problems for code generation, particularly writing EXTRACT/INSERT_SUBREG patterns for converting between the two. The change here switches to classifying VPR64 & VPR128 as RegisterOperands, which are essentially aliases for RegisterClasses with different parsing and printing behaviour. This fits almost exactly with their real status (VPR128 == FPR128 printed strangely, VPR64 == FPR64 printed strangely). llvm-svn: 190665
* Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift ↵Hao Liu2013-09-041-0/+38
| | | | | | | | | | instructions: sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshrun,sqshrn,uqshr,sqrshrn,uqrshrn,sshll,ushll and 4 convert instructions: scvtf,ucvtf,fcvtzs,fcvtzu llvm-svn: 189925
* AArch64: add initial NEON supportTim Northover2013-08-011-1/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. llvm-svn: 187567
* Use a OwningPtr instead of a manual delete.Rafael Espindola2013-07-041-5/+3
| | | | llvm-svn: 185673
* Fix leak. Should bring back the valgrind bot.Rafael Espindola2013-07-041-0/+1
| | | | llvm-svn: 185663
* Remove the Copied parameter from MemoryObject::readBytes.Benjamin Kramer2013-05-241-1/+1
| | | | | | | | | | There was exactly one caller using this API right, the others were relying on specific behavior of the default implementation. Since it's too hard to use it right just remove it and standardize on the default behavior. Defines away PR16132. llvm-svn: 182636
* AArch64: remove post-encoder method from FCMP (immediate) instructions.Tim Northover2013-02-281-0/+16
| | | | | | | | The work done by the post-encoder (setting architecturally unused bits to 0 as required) can be done by the existing operand that covers the "#0.0". This removes at least one use of the discouraged PostEncoderMethod uses. llvm-svn: 176261
* AArch64: add block comments where missingTim Northover2013-02-141-1/+7
| | | | | | Only comments affected. No code change at all. llvm-svn: 175169
* Fix formatting in AArch64 backend.Tim Northover2013-02-051-12/+16
| | | | | | | | | | | This should fix three purely whitespace issues: + 80 column violations. + Tab characters. + TableGen brace placement. No functional changes. llvm-svn: 174370
* Remove cyclic dependency in AArch64 librariesTim Northover2013-02-051-1/+1
| | | | | | | | This moves the bit twiddling and string fiddling functions required by other parts of the backend into a separate library. Previously they resided in AArch64Desc, which created a circular dependency between various components. llvm-svn: 174369
* Remove currently unused register decoder from AArch64.Tim Northover2013-02-011-14/+0
| | | | | | This should fix a warning when building this backend. llvm-svn: 174177
* Add AArch64 as an experimental target.Tim Northover2013-01-311-0/+791
This patch adds support for AArch64 (ARM's 64-bit architecture) to LLVM in the "experimental" category. Currently, it won't be built unless requested explicitly. This initial commit should have support for: + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions (except the late addition CRC instructions). + CodeGen features required for C++03 and C99. + Compilation for the "small" memory model: code+static data < 4GB. + Absolute and position-independent code. + GNU-style (i.e. "__thread") TLS. + Debugging information. The principal omission, currently, is performance tuning. This patch excludes the NEON support also reviewed due to an outbreak of batshit insanity in our legal department. That will be committed soon bringing the changes to precisely what has been approved. Further reviews would be gratefully received. llvm-svn: 174054
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