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authorJiangning Liu <jiangning.liu@arm.com>2013-10-04 09:20:44 +0000
committerJiangning Liu <jiangning.liu@arm.com>2013-10-04 09:20:44 +0000
commitac5fd7e5d3edf3f9c4a686037a62e8661958ee58 (patch)
tree615f8c8bc99d297f953f896468ef7ecbaf890d50 /llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
parentf2b811a618c3c5048a343fd9ba04bc72c57e0033 (diff)
downloadbcm5719-llvm-ac5fd7e5d3edf3f9c4a686037a62e8661958ee58.tar.gz
bcm5719-llvm-ac5fd7e5d3edf3f9c4a686037a62e8661958ee58.zip
Implement aarch64 neon instruction set AdvSIMD (3V elem).
llvm-svn: 191944
Diffstat (limited to 'llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp')
-rw-r--r--llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp12
1 files changed, 12 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index 3baa4b5304c..b9d7c1684d5 100644
--- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -85,6 +85,9 @@ static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
unsigned RegNo, uint64_t Address,
const void *Decoder);
+static DecodeStatus DecodeFPR128LoRegisterClass(llvm::MCInst &Inst,
+ unsigned RegNo, uint64_t Address,
+ const void *Decoder);
static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
unsigned OptionHiS,
@@ -349,6 +352,15 @@ DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus
+DecodeFPR128LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
+ uint64_t Address, const void *Decoder) {
+ if (RegNo > 15)
+ return MCDisassembler::Fail;
+
+ return DecodeFPR128RegisterClass(Inst, RegNo, Address, Decoder);
+}
+
static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
unsigned OptionHiS,
uint64_t Address,
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