bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Expand)	Author	Age	Files	Lines
*	[LoopUnroll] Pass SCEV to getUnrollingPreferences hook. NFCI.	Geoff Berry	2017-06-28	1	-1/+2
*	[AArch64] Inline callee if its target-features are a subset of the caller	Florian Hahn	2017-06-27	1	-0/+3
*	Const correctness for TTI::getRegisterBitWidth	Daniel Neilson	2017-06-12	1	-1/+1
*	Re-commit r302678, fixing PR33053.	Amara Emerson	2017-05-16	1	-0/+3
*	[SLP] Enable 64-bit wide vectorization on AArch64	Adam Nemet	2017-05-15	1	-0/+4
*	Revert r302678 "[AArch64] Enable use of reduction intrinsics."	Hans Wennborg	2017-05-15	1	-3/+0
*	[AArch64] Enable use of reduction intrinsics.	Amara Emerson	2017-05-10	1	-0/+3
*	Add a late IR expansion pass for the experimental reduction intrinsics.	Amara Emerson	2017-05-10	1	-0/+4
*	[AArch64] Consider widening instructions in cost calculations	Matthew Simpson	2017-05-09	1	-0/+3
*	[SystemZ] TargetTransformInfo cost functions implemented.	Jonas Paulsson	2017-04-12	1	-3/+5
*	[CodeGenPrep] move aarch64-type-promotion to CGP	Jun Bum Lim	2017-04-03	1	-0/+4
*	[TargetTransformInfo] Refactor and improve getScalarizationOverhead()	Jonas Paulsson	2017-01-26	1	-4/+0
*	[X86] updating TTI costs for arithmetic instructions on X86\SLM arch.	Mohammed Agabaria	2017-01-11	1	-1/+2
*	Currently isLikelyComplexAddressComputation tries to figure out if the given ...	Mohammed Agabaria	2017-01-05	1	-1/+1
*	Do a sweep over move ctors and remove those that are identical to the default.	Benjamin Kramer	2016-10-20	1	-7/+0
*	[TTI] Add hook for vector extract with extension	Matthew Simpson	2016-04-27	1	-0/+3
*	[LoopDataPrefetch] Add TTI to limit the number of iterations to prefetch ahead	Adam Nemet	2016-03-18	1	-0/+2
*	[LoopDataPrefetch/Aarch64] Allow selective prefetching of large-strided accesses	Adam Nemet	2016-03-18	1	-0/+2
*	[Aarch64] Add pass LoopDataPrefetch for Cyclone	Adam Nemet	2016-03-18	1	-0/+4
*	constify the Function parameter to the TTI creation callback and	Eric Christopher	2015-09-16	1	-1/+1
*	[AArch64] Turn on by default interleaved access vectorization	Silviu Baranga	2015-09-01	1	-0/+2
*	[TTI] Make the cost APIs in TargetTransformInfo consistently use 'int'	Chandler Carruth	2015-08-05	1	-19/+16
*	Make TargetTransformInfo keeping a reference to the Module DataLayout	Mehdi Amini	2015-07-09	1	-20/+4
*	[AArch64] Lower interleaved memory accesses to ldN/stN intrinsics. This patch...	Hao Liu	2015-06-26	1	-0/+5
*	[AArch64] Revert r239711 again. We need to discuss how to share code between ...	Hao Liu	2015-06-15	1	-5/+0
*	[AArch64] Match interleaved memory accesses into ldN/stN instructions.	Hao Liu	2015-06-15	1	-0/+5
*	This reverts commit r239529 and r239514.	Rafael Espindola	2015-06-11	1	-5/+0
*	[AArch64] Match interleaved memory accesses into ldN/stN instructions.	Hao Liu	2015-06-11	1	-0/+5
*	[X86] Disable loop unrolling in loop vectorization pass when VF is 1.	Wei Mi	2015-05-06	1	-1/+1
*	[multiversion] Remove the function parameter from the unrolling	Chandler Carruth	2015-02-01	1	-2/+1
*	[multiversion] Switch the TTI queries from TargetMachine to Subtarget	Chandler Carruth	2015-02-01	1	-1/+1
*	[multiversion] Remove the cached TargetMachine pointer from the	Chandler Carruth	2015-02-01	1	-4/+13
*	[multiversion] Switch all of the targets over to use the	Chandler Carruth	2015-02-01	1	-2/+2
*	[multiversion] Remove a false freedom to leave the TargetMachine pointer	Chandler Carruth	2015-02-01	1	-3/+2
*	[PM] Switch the TargetMachine interface from accepting a pass manager	Chandler Carruth	2015-01-31	1	-0/+140