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path: root/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
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* [COFF, ARM64] Add support for Windows ARM64 COFF formatMandeep Singh Grang2017-06-271-0/+4
* [AArch64] Prefer Bcc to CBZ/CBNZ/TBZ/TBNZ when NZCV flags can be set for "free".Chad Rosier2017-06-231-0/+7
* TargetPassConfig: Keep a reference to an LLVMTargetMachine; NFCMatthias Braun2017-05-301-3/+3
* [AArch64][GlobalISel] Add the Localizer pass for the O0 pipelineQuentin Colombet2017-05-271-1/+9
* [AArch64] Make instruction fusion more aggressive. Florian Hahn2017-05-231-1/+1
* [globalisel][tablegen] Demote OptForSize/OptForMinSize/ForCodeSize to per-fun...Daniel Sanders2017-05-191-5/+2
* [LegacyPassManager] Remove TargetMachine constructorsFrancis Visoiu Mistrih2017-05-181-2/+2
* [AArch64] Remove AArch64AddressTypePromotion passJun Bum Lim2017-05-051-9/+0
* [AArch64] Move GISel accessor initialization from TargetMachine to Subtarget.Quentin Colombet2017-05-011-55/+0
* [globalisel][tablegen] Compute available feature bits correctly.Daniel Sanders2017-04-291-2/+5
* [globalisel][tablegen] Move <Target>InstructionSelector declarations to anony...Daniel Sanders2017-04-061-2/+2
* [CodeGenPrep] move aarch64-type-promotion to CGPJun Bum Lim2017-04-031-1/+1
* [GlobalISel] Add a way for targets to enable GISel.Ahmed Bougacha2017-03-011-0/+11
* [AArch64] Add new target feature to fuse literal generationEvandro Menezes2017-02-011-0/+14
* [CodeGen] Move MacroFusion to the targetEvandro Menezes2017-02-011-1/+2
* Re-commit: [globalisel] Tablegen-erate current Register Bank InformationDaniel Sanders2017-01-191-0/+2
* [AArch64, Lanai] Fix some Clang-tidy modernize and Include What You Use warni...Eugene Zelenko2017-01-061-8/+30
* [GlobalISel] Drop workaround for Legalizer member/class sharing a name. NFC.Ahmed Bougacha2016-12-151-1/+1
* MachineScheduler: Export function to construct "default" scheduler.Matthias Braun2016-11-281-0/+10
* AArch64: Use DeadRegisterDefinitionsPass before regalloc.Matthias Braun2016-11-161-3/+4
* GlobalISel: Fix indentation. NFCDiana Picus2016-11-141-1/+1
* AArch64 ILP32 relocations for assembly and ELFJoel Jones2016-10-241-3/+9
* GlobalISel: rename legalizer components to match others.Tim Northover2016-10-141-6/+6
* GlobalISel: select G_GLOBAL_VALUE uses on AArch64.Tim Northover2016-10-101-1/+1
* Move the global variables representing each Target behind accessor functionMehdi Amini2016-10-091-3/+3
* [AArch64] Avoid generating indexed vector instructions for ExynosSebastian Pop2016-10-081-0/+2
* Move AArch64BranchRelaxation to generic codeMatt Arsenault2016-10-061-2/+2
* Revert "[AArch64] Use the reciprocal estimation machinery"Evandro Menezes2016-09-201-26/+2
* [AArch64] Register passes so they can be run by llcDiana Picus2016-08-011-48/+74
* [GlobalISel] Introduce an instruction selector.Ahmed Bougacha2016-07-271-2/+20
* Fix a GCC error due to this member name also being a type name. ThisChandler Carruth2016-07-231-3/+3
* GlobalISel: implement legalization pass, with just one transformation.Tim Northover2016-07-221-0/+12
* [AArch64] Register AArch64LoadStoreOptimizer so it can be run by llc -run-pas...Geoff Berry2016-07-201-0/+1
* [AArch64] Change the preferred alignment for char and short to word alignment.Chad Rosier2016-07-071-2/+2
* Revert "[AArch64] Change the preferred alignment for char and short to word a...Chad Rosier2016-07-071-2/+2
* fix documentation comment. NFC.Junmo Park2016-07-061-2/+1
* [AArch64] Change the preferred alignment for char and short to word alignmentEvandro Menezes2016-06-211-2/+2
* AArch64: Do not test for CPUs, use SubtargetFeaturesMatthias Braun2016-06-021-2/+1
* Delete Reloc::Default.Rafael Espindola2016-05-181-11/+22
* Trivial cleanups.Rafael Espindola2016-05-181-1/+1
* CodeGen: Move TargetPassConfig from Passes.h to an own header; NFCMatthias Braun2016-05-101-0/+1
* [AArch64] Use the reciprocal estimation machineryEvandro Menezes2016-05-041-2/+27
* [GlobalISel] Move GISelAccessor class into public headersTom Stellard2016-04-141-6/+6
* [AArch64] Get rid of some GlobalISel ifdefs.Quentin Colombet2016-04-071-3/+1
* [GlobalISel] Add RegBankSelect hooks into the pass pipeline.Quentin Colombet2016-04-071-0/+6
* [AArch64] Teach the subtarget how to get to the RegisterBankInfo.Quentin Colombet2016-04-061-0/+28
* AArch64: avoid clobbering SP for dead MOVimm pseudos.Tim Northover2016-04-011-1/+3
* [Aarch64] Turn on the LoopDataPrefetch pass for CycloneAdam Nemet2016-03-301-1/+1
* [Aarch64] Add pass LoopDataPrefetch for CycloneAdam Nemet2016-03-181-0/+13
* [AArch64] Initialize GlobalISel as part of the target initialization.Quentin Colombet2016-03-081-0/+2
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