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| author | Daniel Sanders <daniel_l_sanders@apple.com> | 2017-01-19 11:15:55 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel_l_sanders@apple.com> | 2017-01-19 11:15:55 +0000 |
| commit | d64d5024a4b80d6d909dc34232d024c4f4a86e1e (patch) | |
| tree | 8d7a1ce27b68da29dc55dba8e1427482f8847598 /llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | |
| parent | 207a68985be5cfd592c52fcbc4a8b9cde522aac2 (diff) | |
| download | bcm5719-llvm-d64d5024a4b80d6d909dc34232d024c4f4a86e1e.tar.gz bcm5719-llvm-d64d5024a4b80d6d909dc34232d024c4f4a86e1e.zip | |
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64TargetMachine.cpp')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp index d2883941e2c..9e93833c0a0 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -14,7 +14,9 @@ #include "AArch64CallLowering.h" #include "AArch64InstructionSelector.h" #include "AArch64LegalizerInfo.h" +#ifdef LLVM_BUILD_GLOBAL_ISEL #include "AArch64RegisterBankInfo.h" +#endif #include "AArch64Subtarget.h" #include "AArch64TargetMachine.h" #include "AArch64TargetObjectFile.h" |
