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path: root/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
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* [AArch64] Add support for Cortex-A76 and Cortex-A76AELuke Cheeseman2019-02-251-0/+1
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [AArch64] Refactor the scheduling predicates (1/3) (NFC)Evandro Menezes2018-11-261-4/+4
* [AArch64] Support HiSilicon's TSV110 processorBryan Chan2018-11-091-0/+5
* [AArch64] Sort switch cases (NFC)Evandro Menezes2018-10-311-20/+23
* [AArch64] Support adding X[8-15,18] registers as CSRs.Tri Vo2018-09-221-0/+1
* Verify commit access in fixing typoCalixte Denizet2018-09-191-1/+1
* [AArch64] Support reserving x1-7 registers.Nick Desaulniers2018-09-071-1/+5
* [MinGW] Move code for indicating "potentially not DSO local" into shouldAssum...Martin Storsjo2018-09-041-12/+9
* [MinGW] [AArch64] Add stubs for potential automatic dllimported variablesMartin Storsjo2018-09-041-2/+7
* [AArch64] Add Tiny Code Model for AArch64David Green2018-08-221-1/+3
* AArch64: Implement support for the shadowcallstack attribute.Peter Collingbourne2018-04-041-2/+3
* [AArch64] Reserve x18 register on FuchsiaPetr Hosek2018-04-011-2/+2
* [AArch64] Properly handle dllimport of variables when using fast-iselMartin Storsjo2018-01-301-3/+6
* [AArch64] Add pipeline model for Exynos M3Evandro Menezes2018-01-301-0/+6
* AArch64: Fix emergency spillslot being out of reach for large callframesMatthias Braun2018-01-191-0/+10
* Revert "AArch64: Fix emergency spillslot being out of reach for large callfra...Matthias Braun2018-01-101-10/+0
* AArch64: Fix emergency spillslot being out of reach for large callframesMatthias Braun2018-01-101-0/+10
* AArch64/X86: Factor out common bzero logic; NFCMatthias Braun2017-12-181-13/+0
* Remove redundant includes from lib/Target/AArch64.Michael Zolotukhin2017-12-131-4/+0
* [aarch64][globalisel] Define G_ATOMIC_CMPXCHG and G_ATOMICRMW_* and make them...Daniel Sanders2017-11-281-1/+1
* [AArch64] Add basic support for Qualcomm's Saphira CPU.Chad Rosier2017-09-251-0/+5
* [ARM][AArch64] Cortex-A75 and Cortex-A55 supportSam Parker2017-08-211-2/+2
* Reapply "[GlobalISel] Remove the GISelAccessor API."Quentin Colombet2017-08-151-46/+11
* Revert "[GlobalISel] Remove the GISelAccessor API."Quentin Colombet2017-08-081-11/+46
* [GlobalISel] Remove the GISelAccessor API.Quentin Colombet2017-08-041-46/+11
* [GlobalISel] Make GlobalISel a non-optional library.Quentin Colombet2017-08-031-8/+0
* [AArch64] Use 8 bytes as preferred function alignment on Cortex-A53.Florian Hahn2017-07-291-1/+3
* [COFF, ARM64] Reserve X18 register by defaultMandeep Singh Grang2017-07-181-1/+2
* [AArch64] Use 16 bytes as preferred function alignment on Cortex-A73.Florian Hahn2017-07-181-1/+3
* [AArch64] Use 16 bytes as preferred function alignment on Cortex-A57.Florian Hahn2017-07-071-0/+1
* [AArch64] Use 16 bytes as preferred function alignment on Cortex-A72.Florian Hahn2017-07-071-1/+3
* [Falkor] Enable SW Prefetch.Haicheng Wu2017-06-121-0/+4
* Revert r291254: [AArch64] Reduce vector insert/extract cost for FalkorMatthew Simpson2017-05-241-1/+0
* [globalisel][tablegen] Demote OptForSize/OptForMinSize/ForCodeSize to per-fun...Daniel Sanders2017-05-191-3/+2
* [SLP] Enable 64-bit wide vectorization on AArch64Adam Nemet2017-05-151-0/+8
* [AArch64] Move GISel accessor initialization from TargetMachine to Subtarget.Quentin Colombet2017-05-011-1/+64
* [globalisel][tablegen] Compute available feature bits correctly.Daniel Sanders2017-04-291-2/+3
* AArch64: put nonlazybind special handling behind a flag for now.Tim Northover2017-04-171-1/+6
* AArch64: support nonlazybindTim Northover2017-04-171-0/+17
* [AArch64][Fuchsia] Allow -mcmodel=kernel for --target=aarch64-fuchsiaPetr Hosek2017-04-041-3/+3
* [AArch64] Vulcan is now ThunderXT99Joel Jones2017-03-071-3/+9
* [AArch64] Add Cavium ThunderX supportJoel Jones2017-02-171-0/+8
* [AArch64] Reduce vector insert/extract cost for Falkor.Chad Rosier2017-01-061-0/+1
* [AArch64] Set the max interleave factor for Falkor.Chad Rosier2016-11-221-1/+3
* [AArch64] Add support for Qualcomm's Falkor CPU.Chad Rosier2016-11-151-0/+1
* [AArch64] Adjust the cost model for Exynos M1.Evandro Menezes2016-10-251-1/+1
* Set the vectorizer MaxInterleaveFactor for Exynos.Abderrazek Zaafrani2016-10-211-0/+1
* GlobalISel: rename legalizer components to match others.Tim Northover2016-10-141-2/+2
* AArch64Subtarget: Remove unused CPUString fieldMatthias Braun2016-10-031-3/+4
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