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path: root/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
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* GlobalISel: allow truncating pointer casts on AArch64.Tim Northover2016-10-311-1/+1
| | | | llvm-svn: 285615
* GlobalISel: translate stack protector intrinsicsTim Northover2016-10-311-3/+12
| | | | llvm-svn: 285614
* GlobalISel: select small binary operations on AArch64.Tim Northover2016-10-181-4/+9
| | | | | | | | AArch64 actually supports many 8-bit operations under the definition used by GlobalISel: the designated information-carrying bits of a GPR32 get the right value if you just use the normal 32-bit instruction. llvm-svn: 284526
* GlobalISel: support floating-point constants on AArch64.Tim Northover2016-10-181-7/+74
| | | | | | Patch from Ahmed Bougacha. llvm-svn: 284523
* GlobalISel: support wider range of load/store sizes in AArch64.Tim Northover2016-10-171-0/+8
| | | | llvm-svn: 284406
* GlobalISel: support G_TRUNC selection on AArch64.Tim Northover2016-10-121-0/+80
| | | | | | Ahmed's patch again. llvm-svn: 284075
* GlobalISel: support int <-> float conversions on AArch64.Tim Northover2016-10-121-1/+95
| | | | | | More of Ahmed's work. llvm-svn: 284074
* GlobalISel: select G_FCMP instructions on AArch64.Tim Northover2016-10-121-0/+116
| | | | | | Another of Ahmed's patches. llvm-svn: 284073
* GlobalISel: support selection of G_ICMP on AArch64.Tim Northover2016-10-121-0/+71
| | | | | | Patch from Ahmed Bougaca again. llvm-svn: 284072
* GlobalISel: select G_BRCOND instructions on AArch64.Tim Northover2016-10-121-0/+22
| | | | llvm-svn: 284071
* [AArch64][InstrustionSelector] Teach the selector about G_BITCAST.Quentin Colombet2016-10-121-59/+2
| | | | llvm-svn: 283973
* [AArch64][InstructionSelector] Refactor the handling of copies.Quentin Colombet2016-10-121-26/+83
| | | | | | | | | | | | | | Although Copies are not specific to preISel, we still have to assign them a proper register class. However, given they are not constrained to anything we do not have to handle the source register at the copy. It will be properly mapped when reaching the related definition. In the process, the handlong of G_ANYEXT is slightly modified as those end up being selected as copy. The difference is that when register size do not match on both sides, we need to insert SUBREG_TO_REG operation, otherwise the post RA copy expansion will not be happy! llvm-svn: 283972
* GlobalISel: support same-size casts on AArch64.Tim Northover2016-10-111-0/+62
| | | | | | | Mostly Ahmed's work again, I'm just sprucing things up slightly before committing. llvm-svn: 283952
* GlobalISel: support selection of extend operations.Tim Northover2016-10-111-0/+99
| | | | | | Patch mostly by Ahmed Bougaca. llvm-svn: 283937
* [AArch64][InstructionSelector] Teach how to select FP load/store.Quentin Colombet2016-10-111-0/+7
| | | | | | This patch allows to select 32 and 64-bit FP load and store. llvm-svn: 283832
* [AArch64][InstructionSelector] Teach the selector how to handle vector OR.Quentin Colombet2016-10-111-0/+2
| | | | | | | | | | This only adds the support for 64-bit vector OR. Adding more sizes is not difficult, but it requires a bigger refactoring because ORs work on any size, not necessarly the ones that match the width of the register width. Right now, this is not expressed in the legalization, so don't bother pushing the refactoring yet. llvm-svn: 283831
* GlobalISel: select G_GLOBAL_VALUE uses on AArch64.Tim Northover2016-10-101-2/+24
| | | | llvm-svn: 283809
* GlobalISel: support selecting G_GEP instructions.Tim Northover2016-10-101-1/+3
| | | | | | They're basically just an alias for G_ADD on AArch64. llvm-svn: 283807
* GlobalISel: support selecting constants on AArch64.Tim Northover2016-10-101-0/+10
| | | | llvm-svn: 283806
* GlobalISel: remove "unsized" LLTTim Northover2016-09-151-5/+4
| | | | | | | | It was only really there as a sentinel when instructions had to have precisely one type. Now that registers are typed, each register really has to have a type that is sized. llvm-svn: 281599
* GlobalISel: cache pointer sizes in LLTTim Northover2016-09-151-4/+4
| | | | | | | Otherwise everything that needs to work out what size they are has to keep a DataLayout handy, which is a bit silly and very annoying. llvm-svn: 281597
* GlobalISel: remove G_TYPE and G_PHITim Northover2016-09-091-10/+0
| | | | | | | | These instructions were only necessary when type information was stored in the MachineInstr (because only generic MachineInstrs possessed a type). Now that it's in MachineRegisterInfo, COPY and PHI work fine. llvm-svn: 281037
* GlobalISel: move type information to MachineRegisterInfo.Tim Northover2016-09-091-15/+10
| | | | | | | | | | | | | | | | | We want each register to have a canonical type, which means the best place to store this is in MachineRegisterInfo rather than on every MachineInstr that happens to use or define that register. Most changes following from this are pretty simple (you need an MRI anyway if you're going to be doing any transformations, so just check the type there). But legalization doesn't really want to check redundant operands (when, for example, a G_ADD only ever has one type) so I've made use of MCInstrDesc's operand type field to encode these constraints and limit legalization's work. As an added bonus, more validation is possible, both in MachineVerifier and MachineIRBuilder (coming soon). llvm-svn: 281035
* GlobalISel: add a G_PHI instruction to give phis a type.Tim Northover2016-09-011-0/+6
| | | | | | | They're another source of generic vregs, which are going to need a type on the definition when we remove the register width from MachineRegisterInfo. llvm-svn: 280412
* GlobalISel: use G_TYPE to annotate physregs with a type.Tim Northover2016-08-311-1/+6
| | | | | | | | | | More preparation for dropping source types from MachineInstrs: regsters coming out of already-selected code (i.e. non-generic instructions) don't have a type, but that information is needed so we must add it manually. This is done via a new G_TYPE instruction. llvm-svn: 280292
* [AArch64][GlobalISel] Select floating-point binary ops.Ahmed Bougacha2016-08-181-0/+34
| | | | | | There is no FREM instruction, but the others are straightforward. llvm-svn: 279081
* [AArch64][GlobalISel] Select G_SDIV/G_UDIV.Ahmed Bougacha2016-08-181-0/+10
| | | | | | | | There is no REM instruction; that will require an expansion. It's not obvious that should be done in select, rather than as a (custom?) legalization. llvm-svn: 279074
* [AArch64][GlobalISel] Select G_MUL.Ahmed Bougacha2016-08-161-0/+37
| | | | llvm-svn: 278810
* [AArch64][GlobalISel] Factor out unsupported binop check. NFC.Ahmed Bougacha2016-08-161-40/+50
| | | | | | | We're going to need it for G_MUL, and, if other targets end up using something similar, we can easily put it in the generic selector. llvm-svn: 278808
* [AArch64][GlobalISel] Select (variable) shifts.Ahmed Bougacha2016-08-161-0/+15
| | | | | | For now, no support for immediates. llvm-svn: 278804
* [AArch64][GlobalISel] Select p0 G_FRAME_INDEX.Ahmed Bougacha2016-08-161-0/+18
| | | | | | And mark it as legal. llvm-svn: 278802
* [AArch64][GlobalISel] Select G_XOR.Ahmed Bougacha2016-07-291-0/+5
| | | | llvm-svn: 277173
* [AArch64][GlobalISel] Select G_LOAD/G_STORE.Ahmed Bougacha2016-07-291-0/+56
| | | | | | | | | | Mostly straightforward as we ignore addressing modes and just use the base + unsigned immediate offset (always 0) variants. This currently fails to select extloads because we have yet to agree on a representation. llvm-svn: 277171
* [AArch64][GlobalISel] Select G_BR.Ahmed Bougacha2016-07-281-8/+13
| | | | | | | This is the first unsized instruction we support; move down the 'sized' check to binops. llvm-svn: 277007
* [AArch64][GlobalISel] Select GPR G_SUB.Ahmed Bougacha2016-07-281-1/+6
| | | | llvm-svn: 277003
* [AArch64][GlobalISel] Select GPR G_AND.Ahmed Bougacha2016-07-281-0/+5
| | | | llvm-svn: 277002
* [GlobalISel] Remove types on selected insts instead of using LLT().Ahmed Bougacha2016-07-281-1/+1
| | | | | | | | | | LLT() has a particular meaning: it's one invalid type. But we really want selected instructions to have no type whatsoever. Also verify that types don't linger after ISel, and enable the verifier on the AArch64 select test. llvm-svn: 277001
* [GlobalISel] Introduce an instruction selector.Ahmed Bougacha2016-07-271-0/+162
And implement it for AArch64, supporting x/w ADD/OR. Differential Revision: https://reviews.llvm.org/D22373 llvm-svn: 276875
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