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* Add missing 'override' keyword.Craig Topper2014-11-281-1/+1
| | | | llvm-svn: 222911
* AArch64: treat [N x Ty] as a block during procedure calls.Tim Northover2014-11-271-0/+4
| | | | | | | | | | | | | | The AAPCS treats small structs and homogeneous floating (or vector) aggregates specially, and guarantees they either get passed as a contiguous block of registers, or prevent any future use of those registers and get passed on the stack. This concept can fit quite neatly into LLVM's own type system, mapping an HFA to [N x float] and so on, and small structs to [N x i64]. Doing so allows front-ends to emit AAPCS compliant code without having to duplicate the register counting logic. llvm-svn: 222903
* DAGCombiner: Allow the DAGCombiner to combine multiple FDIVs with the same ↵Hao Liu2014-11-211-0/+1
| | | | | | | | | | | | divisor info FMULs by the reciprocal. E.g., ( a / D; b / D ) -> ( recip = 1.0 / D; a * recip; b * recip) A hook is added to allow the target to control whether it needs to do such combine. Reviewed in http://reviews.llvm.org/D6334 llvm-svn: 222510
* [AArch64] Generate vector signed/unsigned mul and mla/mls long.Chad Rosier2014-10-081-0/+3
| | | | | | | Phabricator Revision: http://reviews.llvm.org/D5589 Patch by Balaram Makam <bmakam@codeaurora.org>!! llvm-svn: 219276
* constify TargetMachine parameter.Eric Christopher2014-10-031-1/+1
| | | | llvm-svn: 218934
* [X86] Use the generic AtomicExpandPass instead of X86AtomicExpandPassRobin Morisset2014-09-171-0/+1
| | | | | | | | | | | | This required a new hook called hasLoadLinkedStoreConditional to know whether to expand atomics to LL/SC (ARM, AArch64, in a future patch Power) or to CmpXchg (X86). Apart from that, the new code in AtomicExpandPass is mostly moved from X86AtomicExpandPass. The main result of this patch is to get rid of that pass, which had lots of code duplicated with AtomicExpandPass. llvm-svn: 217928
* AArch64: fix big-endian immediate materialisationTim Northover2014-09-041-0/+7
| | | | | | | | | | | | We were materialising big-endian constants using DAG nodes with types different from what was requested, followed by a bitcast. This is fine on little-endian machines where bitcasting is a nop, but we need a slightly different representation for big-endian. This adds a new set of NVCAST (natural-vector cast) operations which are always nops. Patch by Asiri Rathnayake. llvm-svn: 217138
* Refactor AtomicExpandPass and add a generic isAtomic() method to InstructionRobin Morisset2014-09-031-1/+3
| | | | | | | | | | | | | | | | | | | | | Summary: Split shouldExpandAtomicInIR() into different versions for Stores/Loads/RMWs/CmpXchgs. Makes runOnFunction cleaner (no more redundant checking/casting), and will help moving the X86 backend to this pass. This requires a way of easily detecting which instructions are atomic. I followed the pattern of mayReadFromMemory, mayWriteOrReadMemory, etc.. in making isAtomic() a method of Instruction implemented by a switch on the opcodes. Test Plan: make check Reviewers: jfb Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D5035 llvm-svn: 217080
* Add override to overriden virtual methods, remove virtual keywords.Benjamin Kramer2014-09-031-1/+1
| | | | | | No functionality change. Changes made by clang-tidy + some manual cleanup. llvm-svn: 217028
* Fix typos in comments, NFCRobin Morisset2014-08-291-2/+1
| | | | | | | | | | | | | | Summary: Just fixing comments, no functional change. Test Plan: N/A Reviewers: jfb Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D5130 llvm-svn: 216784
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-3/+3
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* Add alignment value to allowsUnalignedMemoryAccessMatt Arsenault2014-07-271-3/+4
| | | | | | | | | | Rename to allowsMisalignedMemoryAccess. On R600, 8 and 16 byte accesses are mostly OK with 4-byte alignment, and don't need to be split into multiple accesses. Vector loads with an alignment of the element type are not uncommon in OpenCL code. llvm-svn: 214055
* [stack protector] Fix a potential security bug in stack protector where theAkira Hatanaka2014-07-251-0/+1
| | | | | | | | | | | | | | address of the stack guard was being spilled to the stack. Previously the address of the stack guard would get spilled to the stack if it was impossible to keep it in a register. This patch introduces a new target independent node and pseudo instruction which gets expanded post-RA to a sequence of instructions that load the stack guard value. Register allocator can now just remat the value when it can't keep it in a register. <rdar://problem/12475629> llvm-svn: 213967
* [AArch64] Lower sdiv x, pow2 using add + select + shift.Chad Rosier2014-07-231-0/+3
| | | | | | | | | | | | | | | The target-independent DAGcombiner will generate: asr w1, X, #31 w1 = splat sign bit. add X, X, w1, lsr #28 X = X + 0 or pow2-1 asr w0, X, asr #4 w0 = X/pow2 However, the add + shifts is expensive, so generate: add w0, X, 15 w0 = X + pow2-1 cmp X, wzr X - 0 csel X, w0, X, lt X = (X < 0) ? X + pow2-1 : X; asr w0, X, asr 4 w0 = X/pow2 llvm-svn: 213758
* [codegen,aarch64] Add a target hook to the code generator to controlChandler Carruth2014-07-031-0/+3
| | | | | | | | | | | | | | | | | | | | | vector type legalization strategies in a more fine grained manner, and change the legalization of several v1iN types and v1f32 to be widening rather than scalarization on AArch64. This fixes an assertion failure caused by scalarizing nodes like "v1i32 trunc v1i64". As v1i64 is legal it will fail to scalarize v1i32. This also provides a foundation for other targets to have more granular control over how vector types are legalized. Patch by Hao Liu, reviewed by Tim Northover. I'm committing it to allow some work to start taking place on top of this patch as it adds some really important hooks to the backend that I'd like to immediately start using. =] http://reviews.llvm.org/D4322 llvm-svn: 212242
* Move AArch64TargetLowering to AArch64Subtarget.Eric Christopher2014-06-101-1/+1
| | | | | | | This currently necessitates a TargetMachine for the TargetLowering constructor and TLOF. llvm-svn: 210605
* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-241-0/+464
| | | | | | | | | | | | | | | This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
* AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.Tim Northover2014-05-241-410/+0
| | | | | | | | | | | | | | | | I'm doing this in two phases for a better "git blame" record. This commit removes the previous AArch64 backend and redirects all functionality to ARM64. It also deduplicates test-lines and removes orphaned AArch64 tests. The next step will be "git mv ARM64 AArch64" and rewire most of the tests. Hopefully LLVM is still functional, though it would be even better if no-one ever had to care because the rename happens straight afterwards. llvm-svn: 209576
* Revert "Implement global merge optimization for global variables."Rafael Espindola2014-05-161-4/+0
| | | | | | | | | | | | This reverts commit r208934. The patch depends on aliases to GEPs with non zero offsets. That is not supported and fairly broken. The good news is that GlobalAlias is being redesigned and will have support for offsets, so this patch should be a nice match for it. llvm-svn: 208978
* Implement global merge optimization for global variables.Jiangning Liu2014-05-151-0/+4
| | | | | | | | | | | This commit implements two command line switches -global-merge-on-external and -global-merge-aligned, and both of them are false by default, so this optimization is disabled by default for all targets. For ARM64, some back-end behaviors need to be tuned to get this optimization further enabled. llvm-svn: 208934
* Pass the value type to TLI::getRegisterByNameHal Finkel2014-05-111-1/+1
| | | | | | | | | | | | | We must validate the value type in TLI::getRegisterByName, because if we don't and the wrong type was used with the IR intrinsic, then we'll assert (because we won't be able to find a valid register class with which to construct the requested copy operation). For PPC64, additionally, the type information is necessary to decide between the 64-bit register and the 32-bit subregister. No functionality change. llvm-svn: 208508
* Add 'override' to getRegisterByName in *ISelLowering.hHal Finkel2014-05-111-1/+1
| | | | | | No functionality change intended. llvm-svn: 208507
* Implememting named register intrinsicsRenato Golin2014-05-061-0/+2
| | | | | | | | | | | This patch implements the infrastructure to use named register constructs in programs that need access to specific registers (bare metal, kernels, etc). So far, only the stack pointer is supported as a technology preview, but as it is, the intrinsic can already support all non-allocatable registers from any architecture. llvm-svn: 208104
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-22/+26
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. AArch64 edition llvm-svn: 207510
* [AArch64] Enable global merge pass.Jiangning Liu2014-04-221-0/+4
| | | | llvm-svn: 206861
* This commit enables unaligned memory accesses of vector types on AArch64 ↵Jiangning Liu2014-04-181-0/+6
| | | | | | | | back end. This should boost vectorized code performance. Patched by Z. Zheng llvm-svn: 206557
* [AArch64] Implement the isLegalAddressingMode and getScalingFactorCost APIs.Chad Rosier2014-04-121-0/+11
| | | | llvm-svn: 206089
* [AArch64] Implement the isZExtFree APIs.Chad Rosier2014-04-091-0/+4
| | | | llvm-svn: 205926
* [AArch64] Implement the isTruncateFree API.Chad Rosier2014-04-091-0/+4
| | | | | | | | | In AArch64 i64 to i32 truncate operation is a subregister access. This allows more opportunities for LSR optmization to eliminate variables of different types (i32 and i64). llvm-svn: 205925
* [AArch64] Lower SHL_PARTS, SRA_PARTS and SRL_PARTSLogan Chien2014-03-271-0/+3
| | | | | | | | Lower SHL_PARTS, SRA_PARTS and SRL_PARTS to perform 128-bit integer shift Patch by GuanHong Liu. llvm-svn: 204940
* Switch all uses of LLVM_OVERRIDE to just use 'override' directly.Craig Topper2014-03-021-2/+2
| | | | llvm-svn: 202621
* [AArch64 NEON] Try to generate CONCAT_VECTOR when lowering BUILD_VECTOR or ↵Kevin Qin2014-01-271-1/+5
| | | | | | | | SHUFFLE_VECTOR. Replace r199791. llvm-svn: 200180
* Revert r199791.Kevin Qin2014-01-271-5/+1
| | | | | | It's old version which has some bugs. I'll commit lattest patch soon. llvm-svn: 200179
* fix some spell mistakes around 'ConcatVector' and 'ShuffleVector' in AArch64 ↵Kevin Qin2014-01-231-1/+1
| | | | | | backend. llvm-svn: 199858
* [AArch64 NEON] Try to generate CONCAT_VECTOR when lowering BUILD_VECTOR or ↵Kevin Qin2014-01-221-1/+5
| | | | | | SHUFFLE_VECTOR. llvm-svn: 199791
* Re-sort all of the includes with ./utils/sort_includes.py so thatChandler Carruth2014-01-071-1/+1
| | | | | | | | | | subsequent changes are easier to review. About to fix some layering issues, and wanted to separate out the necessary churn. Also comment and sink the include of "Windows.h" in three .inc files to match the usage in Memory.inc. llvm-svn: 198685
* Remove the 's' DataLayout specificationRafael Espindola2014-01-011-0/+2
| | | | | | | | | | | | | | | | | | | | | | | During the years there have been some attempts at figuring out how to align byval arguments. A look at the commit log suggests that they were * Use the ABI alignment. * When that was not sufficient for x86-64, I added the 's' specification to DataLayout. * When that was not sufficient Evan added the virtual getByValTypeAlignment. * When even that was not sufficient, we just got the FE to add the alignment to the byval. This patch is just a simple cleanup that removes my first attempt at fixing the problem. I also added an AArch64 implementation of getByValTypeAlignment to make sure this patch is a nop. I also left the 's' parsing for backward compatibility. I will send a short email to llvmdev about the change for anyone maintaining an out of tree target. llvm-svn: 198287
* [AArch64 NEON]Implment loading vector constant form constant pool.Kevin Qin2013-12-181-0/+2
| | | | llvm-svn: 197551
* [AArch64 NEON] Get instruction BSL matched to VSELECT.Kevin Qin2013-12-111-3/+0
| | | | llvm-svn: 196998
* For AArch64, add missing register cost calculation for big value types like ↵Jiangning Liu2013-12-051-0/+4
| | | | | | v4i64 and v8i64. llvm-svn: 196456
* Refactored the implementation of AArch64 NEON instruction ZIP, UZPKevin Qin2013-11-261-0/+10
| | | | | | | and TRN. Fix a bug when mixed use of vget_high_u8() and vuzp_u8(). llvm-svn: 195716
* Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.Hao Liu2013-11-191-2/+22
| | | | llvm-svn: 195078
* Implement the newly added ACLE functions for ld1/st1 with 2/3/4 vectors.Hao Liu2013-11-181-1/+7
| | | | | | The functions are like: vst1_s8_x2 ... llvm-svn: 194990
* Implement aarch64 neon instruction class SIMD misc.Kevin Qin2013-11-141-0/+5
| | | | llvm-svn: 194656
* Implement AArch64 Neon instruction set Bitwise Extract.Jiangning Liu2013-11-061-0/+3
| | | | llvm-svn: 194118
* Implement AArch64 post-index vector load/store multiple N-element structure ↵Hao Liu2013-11-051-1/+13
| | | | | | | | | | | | class SIMD(lselem-post). Including following 14 instructions: 4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4). llvm-svn: 194043
* [AArch64] Implement FrameAddr and ReturnAddrWeiming Zhao2013-10-291-0/+2
| | | | | | Fixes PR17690 llvm-svn: 193625
* Implement aarch64 neon instruction set AdvSIMD (copy).Kevin Qin2013-10-111-3/+7
| | | | llvm-svn: 192410
* Implement AArch64 vector load/store multiple N-element structure class ↵Hao Liu2013-10-101-0/+4
| | | | | | | | | | | | SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4). llvm-svn: 192361
* Revert "Implement AArch64 vector load/store multiple N-element structure ↵Rafael Espindola2013-10-101-4/+0
| | | | | | | | class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)." This reverts commit r192352. It broke the build. llvm-svn: 192354
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