Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.

llvm-svn: 195078

1 files changed, 22 insertions, 2 deletions

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 0f30a7a9d2e..a51d10f01cf 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -152,8 +152,13 @@ namespace AArch64ISD {
     // Vector extract
     NEON_VEXTRACT,
 
+    // NEON duplicate lane loads
+    NEON_LD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
+    NEON_LD3DUP,
+    NEON_LD4DUP,
+
     // NEON loads with post-increment base updates:
-    NEON_LD1_UPD = ISD::FIRST_TARGET_MEMORY_OPCODE,
+    NEON_LD1_UPD,
     NEON_LD2_UPD,
     NEON_LD3_UPD,
     NEON_LD4_UPD,
@@ -168,7 +173,22 @@ namespace AArch64ISD {
     NEON_ST4_UPD,
     NEON_ST1x2_UPD,
     NEON_ST1x3_UPD,
-    NEON_ST1x4_UPD
+    NEON_ST1x4_UPD,
+
+    // NEON duplicate lane loads with post-increment base updates:
+    NEON_LD2DUP_UPD,
+    NEON_LD3DUP_UPD,
+    NEON_LD4DUP_UPD,
+
+    // NEON lane loads with post-increment base updates:
+    NEON_LD2LN_UPD,
+    NEON_LD3LN_UPD,
+    NEON_LD4LN_UPD,
+
+    // NEON lane store with post-increment base updates:
+    NEON_ST2LN_UPD,
+    NEON_ST3LN_UPD,
+    NEON_ST4LN_UPD
   };
 }