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path: root/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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* [SelectionDAG] Allow targets to specify legality of extloads' resultAhmed Bougacha2015-01-081-10/+16
* [CodeGen] Use MVT iterator_ranges in legality loops. NFC intended.Ahmed Bougacha2015-01-071-20/+15
* ARM: permit tail calls to weak externals on COFFSaleem Abdulrasool2015-01-031-1/+3
* [AArch64] MachO large code-model: Materialize FP constants in code.Juergen Ributzka2014-12-101-0/+7
* AArch64: use explicit MVT::i64 when creating EXTRACT_SUBVECTOR nodes.Tim Northover2014-12-061-10/+12
* [AArch64] Combining Load and IntToFp should check for neon availabilityWeiming Zhao2014-12-041-3/+4
* AArch64: fix wrong-endian parameter passing.Tim Northover2014-12-031-2/+4
* [AArch64] Don't combine "select (setcc i1 LHS, RHS), vL, vR".Ahmed Bougacha2014-12-011-0/+6
* [AArch64] Fix v2i8->i16 bitcast legalization.Ahmed Bougacha2014-12-011-5/+4
* AArch64: treat [N x Ty] as a block during procedure calls.Tim Northover2014-11-271-0/+6
* DAGCombiner: Allow the DAGCombiner to combine multiple FDIVs with the same di...Hao Liu2014-11-211-0/+6
* Fix more instances of -Wsentinel on Windows with s/NULL/nullptr/Reid Kleckner2014-11-201-1/+1
* [Aarch64] Customer lowering of CTPOP to SIMD should check for NEON availabilityWeiming Zhao2014-11-191-0/+3
* We can get the TLOF from the TargetMachine - so constructor no longer require...Aditya Nandakumar2014-11-131-1/+1
* This patch changes the ownership of TLOF from TargetLoweringBase to TargetMac...Aditya Nandakumar2014-11-131-10/+1
* [AArch64] Fix miscompile of comparison with 0xffffffffffffffffOliver Stannard2014-11-031-4/+4
* [AArch64] Fix a silent codegen fault in BUILD_VECTOR lowering.James Molloy2014-10-171-9/+9
* [AArch64] Fix miscompile of sdiv-by-power-of-2.Juergen Ributzka2014-10-161-1/+1
* [AArch64] Generate vector signed/unsigned mul and mla/mls long.Chad Rosier2014-10-081-0/+200
* Make AAMDNodes ctor and operator bool (!!!) explicit, mop up bugs and weirdne...Benjamin Kramer2014-10-041-1/+1
* constify TargetMachine parameter.Eric Christopher2014-10-031-1/+1
* Add missing natual vector cast.Asiri Rathnayake2014-10-011-0/+1
* [X86] Use the generic AtomicExpandPass instead of X86AtomicExpandPassRobin Morisset2014-09-171-0/+4
* [AArch 64] Use a constant pool load for weak symbol references whenAsiri Rathnayake2014-09-101-1/+21
* AArch64: fix vector-immediate BIC/ORR on big-endian devices.Tim Northover2014-09-041-12/+12
* AArch64: fix big-endian immediate materialisationTim Northover2014-09-041-21/+21
* Refactor AtomicExpandPass and add a generic isAtomic() method to InstructionRobin Morisset2014-09-031-13/+22
* Silencing an MSVC C4334 warning ('<<' : result of 32-bit shift implicitly con...Aaron Ballman2014-09-021-1/+1
* AArch64: Silence -Wabsolute-value warning with std::absReid Kleckner2014-08-291-1/+2
* Fix typos in comments, NFCRobin Morisset2014-08-291-2/+1
* Remove spurious mask operations from AArch64 add->compares on 16 and 8 bit va...Louis Gerbarg2014-08-291-0/+263
* AArch64: only try to get operand of a known node.Tim Northover2014-08-291-5/+5
* AArch64: skip select/setcc combine in complex case.Tim Northover2014-08-291-8/+10
* [AArch64] Fix some failures exposed by value type v4f16 and v8f16.Jiangning Liu2014-08-291-2/+2
* AArch64: More correctly constrain target vector extend lowering.Jim Grosbach2014-08-281-3/+3
* Generate CMN when comparing a short int with minusDavid Xu2014-08-281-3/+41
* Teach the AArch64 backend about v4f16 and v8f16Oliver Stannard2014-08-271-8/+96
* Simplify creation of a bunch of ArrayRefs by using None, makeArrayRef or just...Craig Topper2014-08-271-2/+2
* Hide two different AlignMode enums in anonymous namespaces. This bug is repor...Alexey Samsonov2014-08-191-0/+2
* Make use of isAtLeastRelease/Acquire in the ARM/AArch64 backendsRobin Morisset2014-08-181-4/+2
* Teach the AArch64 backend to handle f16Oliver Stannard2014-08-181-0/+9
* [ARM,AArch64] Do not tail-call to an externally-defined function with weak li...Oliver Stannard2014-08-181-0/+13
* [AArch64] Narrow arguments passed in wrong position on the stack inAmara Emerson2014-08-151-2/+2
* AArch64: Tidy up a few comments.Jim Grosbach2014-08-111-2/+2
* Remove the target machine from CCState. Previously it was only usedEric Christopher2014-08-061-17/+17
* [AArch64] Conditional selects are expensive on out-of-order cores.James Molloy2014-08-061-0/+4
* AArch64: Add support for instruction prefetch intrinsicYi Kong2014-08-051-2/+2
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-4/+8
* [AArch64] Generate tbz/tbnz when comparing against zero.Chad Rosier2014-08-011-10/+16
* Make sure no loads resulting from load->switch DAGCombine are marked invariantLouis Gerbarg2014-07-311-1/+1
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